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1. 发明申请

US20140151864A1 ATOMIC LEVEL BONDING FOR ELECTRONICS PACKAGING 有权
标题翻译：电子包装原子级联
公开(公告)号：US20140151864A1
公开(公告)日：2014-06-05
申请号：US13705269
申请日：2012-12-05
申请人： Ralph S. TAYLOR , Steven E. STALLER
发明人： Ralph S. TAYLOR , Steven E. STALLER
IPC分类号： H01L23/495
CPC分类号： H01L23/49568 , H01L23/36 , H01L23/3735 , H01L23/49531 , H01L23/49562 , H01L23/49575 , H01L23/49844 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/80 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/06181 , H01L2224/08225 , H01L2224/80012 , H01L2224/80203 , H01L2224/80424 , H01L2224/80444 , H01L2224/80447 , H01L2224/80805 , H01L2924/01322 , H01L2924/10253 , H01L2924/10272 , H01L2924/1033 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/3511 , H01L2924/00
摘要： An electronic device assembly that includes a die and a substrate, and optionally a lead frame and a heat spreader. The die is characterized as an electronic device in die form, and has a polished die region. The substrate has a polished substrate region in direct contact with the polished die region. The polished die region and the polished substrate region have surface finishes effective to attach the die to the substrate by way of an atomic bond. The lead-frame has a polished lead-frame region, and the heat spreader has a polished heat spreader region. These polished regions may also be attached to the polished die region or the polished substrate region by way of an atomic bond.
摘要翻译：一种包括管芯和衬底以及可选地引线框架和散热器的电子器件组件。模具的特征在于以模具形式的电子设备，并且具有抛光的模具区域。衬底具有与抛光的裸片区域直接接触的抛光衬底区域。抛光的裸片区域和抛光的衬底区域具有有效的通过原子键将裸片附接到衬底的表面光洁度。引线框架具有抛光的引线框架区域，散热器具有抛光的散热器区域。这些抛光区域也可以通过原子键连接到抛光的裸片区域或抛光的衬底区域。

2. 发明申请

US20070269959A1 Method of aligning mask layers to buried features 审中-公开
标题翻译：将掩模层对准掩埋特征的方法
公开(公告)号：US20070269959A1
公开(公告)日：2007-11-22
申请号：US11434643
申请日：2006-05-16
申请人： John E. Freeman , Steven E. Staller , Troy A. Chase , William J. Baney
发明人： John E. Freeman , Steven E. Staller , Troy A. Chase , William J. Baney
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： B81C3/002 , B81C2201/019
摘要： A method for fabricating microchip devices is provided. The method includes the steps of providing a first planar substrate, locating at least one first alignment feature in the surface of the first planar substrate, and bonding a second substrate to the surface of the first planar substrate. The method further includes the step of aligning subsequent process operations performed on at least one of the first and second substrates to visible alignment features of the first substrate, wherein the visible alignment features are at least one of the first alignment feature and a visible feature that corresponds to the location of the first alignment feature.
摘要翻译：提供了一种用于制造微芯片器件的方法。该方法包括以下步骤：提供第一平面基板，将第一平面基板的表面中的至少一个第一对准特征定位，以及将第二基板接合到第一平面基板的表面。该方法还包括将在第一和第二基板中的至少一个执行的后续处理操作与第一基板的可见对准特征对准的步骤，其中可见对准特征是第一对准特征和可见特征中的至少一个，对应于第一对准特征的位置。

3. 发明授权

US5413955A Method of bonding silicon wafers at temperatures below 500 degrees centigrade for sensor applications 失效
标题翻译：在低于500摄氏度的温度下将硅晶片粘合用于传感器应用的方法
公开(公告)号：US5413955A
公开(公告)日：1995-05-09
申请号：US169117
申请日：1993-12-21
申请人： Han-Sheng Lee , Steven E. Staller , Dan W. Chilcott
发明人： Han-Sheng Lee , Steven E. Staller , Dan W. Chilcott
IPC分类号： G01P15/08 , H01L21/20
CPC分类号： G01P15/0802 , Y10S148/135
摘要： A process for silicon wafer-to-wafer bonding at temperatures lower than 500.degree. C. has been developed. It consists of (1) treating the cleaned surfaces to make them smooth and hydrophilic, (2) initiating the bond by making intimate contact between wafers and (3) enhancing the bond strength at elevated temperatures. This bonding process can be applied to sensor packaging.
摘要翻译：已经开发了在低于500℃的温度下进行硅晶片到晶片接合的工艺。它包括（1）处理清洁的表面以使其光滑和亲水，（2）通过使晶片之间的紧密接触和（3）在升高的温度下增强粘结强度来引发粘合。这种粘合工艺可以应用于传感器包装。

4. 发明授权

US5415726A Method of making a bridge-supported accelerometer structure 失效
标题翻译：制造桥梁加速度计结构的方法
公开(公告)号：US5415726A
公开(公告)日：1995-05-16
申请号：US170955
申请日：1993-12-21
申请人： Steven E. Staller , James H. Logsdon
发明人： Steven E. Staller , James H. Logsdon
IPC分类号： G01P15/04 , G01P15/08 , H01L29/84 , B44C1/22
CPC分类号： G01P15/0802
摘要： This invention includes a method of making a bridge-supported accelerometer structure. A first wafer is worked, preferably by bulk micromachining, to provide a proof mass supported by a thin membrane on all sides. The thin membrane has the same thickness as the bridges to be defined therein. The first wafer is bonded to a second wafer having a cavity formed therein. The first wafer is then worked, preferably by plasma etching, to delineate bridges in the thin membrane. The cavity in the second wafer provides damping of the proof mass which reduced bridge breakage as portions of the thin membrane are removed leaving the final bridge-supported accelerometer structure. Combining the two wafers together prior to delineating the bridge provides for handling and processing of a much less fragile structure than the first wafer alone with bridges delineated therein.
摘要翻译：本发明包括制造桥式加速度计结构的方法。优选通过体积微加工来加工第一晶片，以提供在所有侧面上由薄膜支撑的校验物质。薄膜具有与要限定的桥相同的厚度。第一晶片被结合到其中形成有腔的第二晶片。然后优选通过等离子体蚀刻来加工第一晶片以描绘薄膜中的桥。第二晶片中的空腔提供了防止质量块的阻尼，当薄膜的部分被去除时，减少桥断裂，留下最终的桥式支撑的加速度计结构。在描绘桥之前，将两个晶片组合在一起，提供了处理和处理比仅在其中描绘的桥的单独的第一晶片少得多的脆弱结构。

5. 发明授权

US5221400A Method of making a microaccelerometer having low stress bonds and means for preventing excessive z-axis deflection 失效
标题翻译：制造具有低压力的微型测微仪的方法和防止过大的Z轴偏移的方法
公开(公告)号：US5221400A
公开(公告)日：1993-06-22
申请号：US625397
申请日：1990-12-11
申请人： Steven E. Staller , David W. DeRoo
发明人： Steven E. Staller , David W. DeRoo
IPC分类号： G01P15/12 , G01P15/08
CPC分类号： G01P15/0802 , G01P2015/084 , Y10S73/01
摘要： A microaccelerometer is provided which has a silicon substrate bonded to a silicon capping plate and silicon back plate, wherein the bonds between the three silicon wafers are characterized by a relatively low residual stress level over a wide temperature range. The bonds are formed by means of an appropriate adhesive at a relatively low temperature without degradation to the microaccelerometer. The bonds between the silicon wafers also provide stress relief during use and packaging of the microaccelerometer. With this invention, the damping distance for the proof mass of the microaccelerometer is accurately controllable and stop means are provided for preventing excessive deflection of the proof mass in a direction perpendicular to the plane of the microaccelerometer.

6. 发明授权

US5369057A Method of making and sealing a semiconductor device having an air path therethrough 失效
标题翻译：制造和密封具有穿过其中的空气通道的半导体器件的方法
公开(公告)号：US5369057A
公开(公告)日：1994-11-29
申请号：US169118
申请日：1993-12-21
申请人： Han-Sheng Lee , Steven E. Staller , James H. Logsdon , Dan W. Chilcott
发明人： Han-Sheng Lee , Steven E. Staller , James H. Logsdon , Dan W. Chilcott
IPC分类号： G01P1/02 , G01P15/08 , H01L21/50 , H01L23/13 , H01L21/60
CPC分类号： G01P1/023 , G01P15/0802 , H01L21/50 , H01L23/13 , H01L2924/0002 , Y10T29/49103
摘要： This invention generally relates to the provision of a vent path during the bonding of silicon wafers and the subsequent encapsulation of the individual devices. A double-sided polished silicon wafer is used for the device wafer. The device wafer includes circuitry, thin membranes and metal interconnections. When bonding a bottom wafer to the device wafer, a vented path exists between the wafers. The venting path includes serpentine shape channel formed by interdigitated fingers and cavities. The cavity and the interdigitated patterns can be etched either together or separately into either wafer. A top wafer has a cavity formed therein. When the top device and bottom wafers are bonded together, the venting path is sealed by dipping the device in a sealing liquid. The serpentine path prevents the sealing liquid from reaching the cavity.
摘要翻译：本发明一般涉及在硅晶片的接合期间提供通气路径以及随后的各个装置的封装。用于器件晶圆的双面抛光硅晶片。器件晶片包括电路，薄膜和金属互连。当将底部晶片接合到器件晶片时，在晶片之间存在通气路径。通气路径包括由叉指和空腔形成的蛇形形状通道。空腔和叉指图案可以一起蚀刻或分别蚀刻到任一晶片中。顶部晶片具有形成在其中的空腔。当顶部装置和底部晶片结合在一起时，通过将装置浸入密封液中来密封通气路径。蛇形路径防止密封液到达腔体。

7. 发明授权

US5284057A Microaccelerometer having low stress bonds and means for preventing excessive Z-axis deflection 失效
标题翻译：具有低应力结合的微加速器和用于防止过大的Z轴偏转的装置
公开(公告)号：US5284057A
公开(公告)日：1994-02-08
申请号：US976100
申请日：1992-11-13
申请人： Steven E. Staller , David W. De Roo
发明人： Steven E. Staller , David W. De Roo
IPC分类号： G01P15/12 , G01P15/08
CPC分类号： G01P15/0802 , G01P2015/084 , Y10S73/01
摘要： A microaccelerometer is provided which has a silicon substrate bonded to a silicon capping plate and silicon back plate, wherein the bonds between the three silicon wafers are characterized by a relatively low residual stress level over a wide temperature range. The bonds are formed by means of an appropriate adhesive at a relatively low temperature without degradation to the microaccelerometer. The bonds between the silicon wafers also provide stress relief during use and packaging of the microaccelerometer. With this invention, the damping distance for the proof mass of the microaccelerometer is accurately controllable and stop means are provided for preventing excessive deflection of the proof mass in a direction perpendicular to the plane of the microaccelerometer.
摘要翻译：提供了一种微加速度计，其具有结合到硅封盖板和硅背板的硅衬底，其中三个硅晶片之间的结合的特征在于在宽的温度范围内具有相对较低的残余应力水平。这些键在相对较低的温度下通过适当的粘合剂形成，而不会降解到微加速度计。硅晶片之间的结合也在微加速度计的使用和封装期间提供应力消除。利用本发明，微加速度计的检验质量块的阻尼距离是可以精确控制的，并且提供停止装置以防止证明物质在垂直于微加速度计平面的方向上的过度偏转。

8. 发明授权

US5068203A Method for forming thin silicon membrane or beam 失效
标题翻译：形成薄硅膜或光束的方法
公开(公告)号：US5068203A
公开(公告)日：1991-11-26
申请号：US577656
申请日：1990-09-04
申请人： James H. Logsdon , Steven E. Staller , David W. De Roo , Gerold W. Neudeck
发明人： James H. Logsdon , Steven E. Staller , David W. De Roo , Gerold W. Neudeck
IPC分类号： G01P15/12 , G01L9/00 , G01P15/08 , H01L21/205 , H01L29/84
CPC分类号： G01P15/0802 , G01L9/0042 , Y10T29/49103
摘要： A method is disclosed for forming thin, suspended membranes of epitaxial silicon material. Silicon oxide strips having a predetermined thickness are first formed on a silicon substrate. The gap, or spacing, between adjaceant beams is preferably less than or equal to about 1.4 times the thickness of the silicon oxide strip. The underlying silicon substrate is exposed within these gaps in the silicon oxide layer, thereby the gaps provide a seed hole for subsequent epitaxial growth from the silicon substrate. Epitaxial silicon is grown through the seed holes and then allowed to grow laterally over the silicon oxide strips to form a continuous layer of epitaxial silicon over the silicon oxide strips. The backside of the silicon substrate, or surface opposite the surface having the silicon oxide strips, is then masked to delineate the desired diaphragm and microbridge pattern. The silicon is etched conventionally from the backside. Etching is substantially terminated automatically by the presence of the silicon oxide strips. The thin, single crystal silicon membranes are suitable for use as diaphragms and microbridges in a microaccelerometers or pressure sensor.

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