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1. 发明授权

US06279064B1 System and method for loading commands to a bus, directly loading selective commands while queuing and strictly ordering other commands 失效
标题翻译：将命令加载到总线的系统和方法，在排队时直接加载选择性命令，并严格排序其他命令
公开(公告)号：US06279064B1
公开(公告)日：2001-08-21
申请号：US09562274
申请日：2000-04-29
申请人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
发明人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.
摘要翻译：输入/输出总线桥接器和命令排队系统包括外部中断路由器，用于从总线单元控制器（BUC）接收中断命令，并响应中断结束（EOI），中断返回（INR）和中断重发（IRR）命令。中断路由器包括用于排序EOI命令的第一命令队列和用于排序INR和IRR命令的第二命令队列。先进先出（FIFO）命令队列命令总线内存映射输入输出（MMIO）命令。 EOI命令从第一个命令队列指向FIFO命令队列的输入。 EOI命令和MMIO命令从命令队列引导到输入输出总线，INR和IRR命令从第二个命令队列引导到输入输出总线。以这种方式，维护相对于MMIO访问的EOI命令的严格排序，同时允许INR和IRR命令绕过入队的MMIO访问。

2. 发明授权

US6065088A System and method for interrupt command queuing and ordering 失效
公开(公告)号：US6065088A
公开(公告)日：2000-05-16
申请号：US144580
申请日：1998-08-31
申请人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
发明人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
IPC分类号： G06F13/40 , G06F13/24 , G06F13/26
CPC分类号： G06F13/4027
摘要： An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.

3. 发明授权

US06442634B2 System and method for interrupt command queuing and ordering 有权
标题翻译：用于中断命令排队和排序的系统和方法
公开(公告)号：US06442634B2
公开(公告)日：2002-08-27
申请号：US09860309
申请日：2001-05-18
申请人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
发明人： Timothy C. Bronson , Wai Ling Lee , Vincent P. Zeyak, Jr.
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.
摘要翻译：输入/输出总线桥接器和命令排队系统包括外部中断路由器，用于从总线单元控制器（BUC）接收中断命令，并响应中断结束（EOI），中断返回（INR）和中断重发（IRR）命令。中断路由器包括用于排序EOI命令的第一命令队列和用于排序INR和IRR命令的第二命令队列。先进先出（FIFO）命令队列命令总线内存映射输入输出（MMIO）命令。 EOI命令从第一个命令队列指向FIFO命令队列的输入。 EOI命令和MMIO命令从命令队列引导到输入输出总线，INR和IRR命令从第二个命令队列引导到输入输出总线。以这种方式，维护相对于MMIO访问的EOI命令的严格排序，同时允许INR和IRR命令绕过入队的MMIO访问。

4. 发明申请

US20200083170A1 POWER DELIVERY FOR EMBEDDED INTERCONNECT BRIDGE DEVICES AND METHODS 审中-公开
公开(公告)号：US20200083170A1
公开(公告)日：2020-03-12
申请号：US16451530
申请日：2019-06-25
申请人： Bok Eng Cheah , Jackson Chung Peng Kong , Loke Yip Foo , Wai Ling Lee
发明人： Bok Eng Cheah , Jackson Chung Peng Kong , Loke Yip Foo , Wai Ling Lee
IPC分类号： H01L23/538 , H01L25/16 , H01L21/48 , H01L25/00
摘要： A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.

5. 发明申请

US20200091040A1 STACKED THROUGH-SILICON VIAS FOR MULTI-DEVICE PACKAGES 审中-公开
公开(公告)号：US20200091040A1
公开(公告)日：2020-03-19
申请号：US16451521
申请日：2019-06-25
申请人： Bok Eng Cheah , Choong Kooi Chee , Jackson Chung Peng Kong , Tat Hin Tan , Wai Ling Lee
发明人： Bok Eng Cheah , Choong Kooi Chee , Jackson Chung Peng Kong , Tat Hin Tan , Wai Ling Lee
IPC分类号： H01L23/48 , H01L23/528
摘要： Disclosed embodiments include a multi-chip package that includes a stacked through-silicon via in a first semiconductive device, and the first semiconductive device is face-to-face coupled to a second semiconductive device by the stacked through-silicon via. The stacked through-silicon via includes a first portion that contacts a second portion, and the first portion emerges from an active semiconductive region of the first semiconductive device adjacent a keep-out region.

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