专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08553476B2 Three dimensional memory system with page of data across word lines 有权
标题翻译：三维存储系统，具有跨字线的数据页面
公开(公告)号：US08553476B2
公开(公告)日：2013-10-08
申请号：US13039581
申请日：2011-03-03
申请人： Tianhong Yan , Luca G. Fasoli , Roy E. Scheuerlein
发明人： Tianhong Yan , Luca G. Fasoli , Roy E. Scheuerlein
IPC分类号： G11C7/00
CPC分类号： G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C2213/33 , G11C2213/35 , G11C2213/71
摘要： A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. One page of data is stored across multiple word lines by programming non-volatile storage elements connected to one column of bit lines and multiple word lines while maintaining the selection of the one column of bit lines. In one embodiment, programming non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.
摘要翻译：非易失性存储元件的三维单片存储器阵列包括多个字线和多个位线。多个位线被分组成列。通过编程连接到一列位线和多个字线的非易失性存储元件，同时保持对一列位线的选择，一页数据被存储在多个字线上。在一个实施例中，编程非易失性存储元件包括使用包括存储设备，连接到存储设备的选择电路和提供两个或更多个接口的各个选择的一个或多个电平移位器的选择电路选择性地将位线连接到读出放大器电路。

2. 发明申请

US20120275210A1 NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING 有权
标题翻译：具有双块编程的非易失存储系统
公开(公告)号：US20120275210A1
公开(公告)日：2012-11-01
申请号：US13095779
申请日：2011-04-27
申请人： Tianhong Yan , Tz-yi Liu , Roy E. Scheuerlein
发明人： Tianhong Yan , Tz-yi Liu , Roy E. Scheuerlein
IPC分类号： G11C11/00 , G11C8/08 , G11C7/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0023 , G11C13/003 , G11C2213/71 , G11C2213/73 , G11C2213/77
摘要： A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits.
摘要翻译：公开了一种非易失性存储系统，其包括多个非易失性存储元件块，连接到非易失性存储元件的块的多个字线，使得每个字线连接到非易失性存储元件的相邻块存储元件，连接到非易失性存储元件块的多个位线，多组字线驱动器，使得每组字线驱动器位于两个相邻块之间，用于驱动连接到两个相邻块的字线，全局数据线，与位线选择性通信的本地数据线，一个或多个选择电路，其选择性地将全局数据线连接到选定的本地数据线，并将未选择的本地数据线连接到一个或多个未选位线信号和控制电路与一个或多个选择电路和全局数据线通信。控制电路通过在连接到两个相邻块的字线上应用编程信号并经由全局数据线和一个或多个选择电路在适当的位线上施加编程信号来同时对两个相邻块的非易失性存储元件进行编程。

3. 发明申请

US20120224410A1 THREE DIMENSIONAL MEMORY SYSTEM WITH INTELLIGENT SELECT CIRCUIT 有权
标题翻译：具有智能选择电路的三维存储器系统
公开(公告)号：US20120224410A1
公开(公告)日：2012-09-06
申请号：US13039593
申请日：2011-03-03
申请人： Tianhong Yan
发明人： Tianhong Yan
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C7/1012 , G11C5/025 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C2207/002 , G11C2213/71
摘要： A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. Performing memory operation on the non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.
摘要翻译：非易失性存储元件的三维单片存储器阵列包括多个字线和多个位线。多个位线被分组成列。对非易失性存储元件执行存储器操作包括使用包括存储设备，连接到存储设备的选择电路和一个或多个电平移位器的选择电路选择性地连接位线到读出放大器，该电平移位器提供两个或更多个接口到相应的选择电路。

4. 发明申请

US20120170346A1 MEMORY SYSTEM WITH SECTIONAL DATA LINES 有权
标题翻译：具有数据线的存储系统
公开(公告)号：US20120170346A1
公开(公告)日：2012-07-05
申请号：US13362311
申请日：2012-01-31
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02
CPC分类号： G11C16/24 , G11C13/0028
摘要： The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
摘要翻译：该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。每个一个或多个块的集合包括一组本地数据线。每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

5. 发明申请

US20090323392A1 SMART DETECTION CIRCUIT FOR WRITING TO NON-VOLATILE STORAGE 有权
标题翻译：用于写入非易失性存储的智能检测电路
公开(公告)号：US20090323392A1
公开(公告)日：2009-12-31
申请号：US12339327
申请日：2008-12-19
申请人： Luca G. Fasoli , Tianhong Yan , Jeffrey Koon Yee Lee
发明人： Luca G. Fasoli , Tianhong Yan , Jeffrey Koon Yee Lee
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0066 , G11C2213/32 , G11C2213/72
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于检测可逆电阻的设置和复位的电路开关元件

6. 发明授权

US08982597B2 Memory system with sectional data lines 有权
标题翻译：具有分段数据线的存储器系统
公开(公告)号：US08982597B2
公开(公告)日：2015-03-17
申请号：US13362320
申请日：2012-01-31
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02 , G11C16/24 , G11C13/00
CPC分类号： G11C16/24 , G11C13/0028
摘要： The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
摘要翻译：该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。每个一个或多个块的集合包括一组本地数据线。每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

7. 发明授权

US08351236B2 Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture 有权
公开(公告)号：US08351236B2
公开(公告)日：2013-01-08
申请号：US12748260
申请日：2010-03-26
申请人： Tianhong Yan , George Samachisa
发明人： Tianhong Yan , George Samachisa
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/06035 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C13/025 , G11C16/10 , G11C2013/0045 , G11C2013/0088 , G11C2213/19 , G11C2213/32 , G11C2213/34 , G11C2213/55 , G11C2213/71 , G11C2213/75 , G11C2213/78 , H01L23/528 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/148 , H01L45/149
摘要： A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

8. 发明授权

US08279650B2 Memory system with data line switching scheme 有权
标题翻译：具有数据线切换方案的存储系统
公开(公告)号：US08279650B2
公开(公告)日：2012-10-02
申请号：US12563139
申请日：2009-09-20
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02 , G11C11/00 , G11C5/06
CPC分类号： G11C8/12 , G11C13/0064 , G11C13/0069 , G11C2013/0066
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selections circuits can change their selections independently of each other. For example, a memory operation is performed concurrently on a first non-volatile storage element of each group of a plurality of groups of non-volatile storage elements. Completion of the memory operation for the first non-volatile storage element of each group is independently detected. A memory operation on a second non-volatile storage element of each group is independently commenced for each group upon independently detecting completion of the memory operation for the first non-volatile storage element of the respective group.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。每个块包括用于选择性地将第一类型的阵列线（例如位线）的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到连接到控制电路的全局数据线的第二选择电路的子集。为了提高存储器操作的性能，第二选择电路可以彼此独立地改变它们的选择。例如，在多组非易失性存储元件的每组的第一非易失性存储元件上同时执行存储器操作。独立检测每组的第一非易失性存储元件的存储器操作的完成。在独立地检测对相应组的第一非易失性存储元件的存储器操作的完成时，对于每个组，在每个组的第二非易失性存储元件上的存储器操作被独立地开始。

9. 发明申请

US20120224408A1 THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE 有权
标题翻译：具有柱管的三维存储系统
公开(公告)号：US20120224408A1
公开(公告)日：2012-09-06
申请号：US13039574
申请日：2011-03-03
申请人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
发明人： Tianhong Yan , Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Tz-yi Liu
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/18 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C17/16
摘要： A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.
摘要翻译：非易失性存储元件的单片三维阵列以块状排列。非易失性存储元件连接到位线和字线。每个块的位线被分组成位线列。位线列包括连接到相应块的顶侧上的选择电路的位线列和连接到相应块的底侧上的选择电路的位线的底列。数据的编程在两列或更多列的位线之间流水线化，以提高编程速度。编程过程的一个实施例包括使用一个或多个选择电路选择性地将两列位线连接到一组或多个选择电路，以选择性地将两列位线中的一列连接到一个或多个信号源，编程用于当前连接到一个或多个信号源的位线列的非易失性存储元件，以及改变连接到一组或多个选择电路的位线的列之一，而另一列位线正在被程序。

10. 发明授权

US08130528B2 Memory system with sectional data lines 有权
标题翻译：具有分段数据线的存储器系统
公开(公告)号：US08130528B2
公开(公告)日：2012-03-06
申请号：US12410648
申请日：2009-03-25
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02 , G11C5/06 , G11C8/00
CPC分类号： G11C16/24 , G11C13/0028
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。块被分组成海湾。存储系统包括与存储元件通信的第一类型的阵列线，与存储元件通信的第二类型的阵列线和读出放大器。每个块在地理上与两个读出放大器相关联，并且特定间隔的所有块共享与特定间隔的块相关联的一组读出放大器。该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。每个一个或多个块的集合包括一组本地数据线。每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式