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1. 发明授权

US08638586B2 Memory system with data line switching scheme 有权
公开(公告)号：US08638586B2
公开(公告)日：2014-01-28
申请号：US13479145
申请日：2012-05-23
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02
CPC分类号： G11C8/12 , G11C13/0064 , G11C13/0069 , G11C2013/0066
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.

2. 发明授权

US08358528B2 Memory system with sectional data lines 有权
标题翻译：具有分段数据线的存储器系统
公开(公告)号：US08358528B2
公开(公告)日：2013-01-22
申请号：US13079613
申请日：2011-04-04
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C16/24 , G11C13/0028
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。块被分组成海湾。存储系统包括与存储元件通信的第一类型的阵列线，与存储元件通信的第二类型的阵列线和读出放大器。每个块在地理上与两个读出放大器相关联，并且特定间隔的所有块共享与特定间隔的块相关联的一组读出放大器。该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。每个一个或多个块的集合包括一组本地数据线。每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

3. 发明申请

US20120257433A1 MEMORY SYSTEM WITH DATA LINE SWITCHING SCHEME 有权
标题翻译：具有数据线切换方案的存储器系统
公开(公告)号：US20120257433A1
公开(公告)日：2012-10-11
申请号：US13479145
申请日：2012-05-23
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02
CPC分类号： G11C8/12 , G11C13/0064 , G11C13/0069 , G11C2013/0066
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。每个块包括用于选择性地将第一类型的阵列线（例如位线）的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到连接到控制电路的全局数据线的第二选择电路的子集。为了提高存储器操作的性能，第二选择电路可以彼此独立地改变它们的选择。

4. 发明申请

US20120170346A1 MEMORY SYSTEM WITH SECTIONAL DATA LINES 有权
标题翻译：具有数据线的存储系统
公开(公告)号：US20120170346A1
公开(公告)日：2012-07-05
申请号：US13362311
申请日：2012-01-31
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02
CPC分类号： G11C16/24 , G11C13/0028
摘要： The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
摘要翻译：该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。每个一个或多个块的集合包括一组本地数据线。每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

5. 发明授权

US08526237B2 Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof 有权
标题翻译：具有读/写元件和读/写电路的3D阵列的非易失性存储器及其方法
公开(公告)号：US08526237B2
公开(公告)日：2013-09-03
申请号：US13151204
申请日：2011-06-01
申请人： George Samachisa , Luca Fasoli , Yan Li , Tianhong Yan
发明人： George Samachisa , Luca Fasoli , Yan Li , Tianhong Yan
IPC分类号： G11C16/06
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C13/0097 , G11C16/06 , G11C2013/0054 , G11C2213/32 , G11C2213/71 , G11C2213/77 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/1675
摘要： A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.
摘要翻译：三维阵列特别适合于响应于在其上施加电压差而可逆地改变电导水平的存储器元件。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。在感测期间，为了补偿字线电阻，读出放大器在对字线的给定位置处的存储元件的感测期间参考存储的参考值。提供了在两个存储器阵列之间具有一行读出放大器的布局以便于参考。当在预定条件下经受偏置电压时，选择的存储元件被复位而不重置相邻的存储元件。

6. 发明申请

US20120287734A1 CONTINUOUS PROGRAMMING OF NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的连续编程
公开(公告)号：US20120287734A1
公开(公告)日：2012-11-15
申请号：US13537029
申请日：2012-06-28
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/12 , G11C13/0007 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete.
摘要翻译：系统将信号驱动器连接到连接到第一非易失性存储元件的第一控制线，在信号驱动器连接到第一控制线的同时对第一控制线进行充电，从而将信号驱动器与第一控制线断开，同时第一控制线保持从信号驱动器充电，将信号驱动器连接到连接到第二非易失性存储元件的第二控制线，在信号驱动器连接到第二控制线的第二控制线上连接到第二非易失性存储元件控制线，并将信号驱动器与第二控制线断开。在不等待第一非易失性存储元件的程序操作完成的情况下，执行信号驱动器与第一控制线的断开，将信号驱动器连接到第二控制线和第二控制线的充电。

7. 发明授权

US08238174B2 Continuous programming of non-volatile memory 有权
标题翻译：连续编程非易失性存储器
公开(公告)号：US08238174B2
公开(公告)日：2012-08-07
申请号：US13217235
申请日：2011-08-24
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C7/22
CPC分类号： G11C7/1078 , G11C7/12 , G11C13/0007 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete.
摘要翻译：非易失性存储系统将信号驱动器连接到连接到第一非易失性存储元件的第一控制线，当信号驱动器连接到第一控制线时，使用信号驱动器对第一控制线充电，断开信号驱动器，而第一控制线保持从信号驱动器充电，将信号驱动器连接到连接到第二非易失性存储元件的第二控制线，使用信号驱动器对第二控制线进行充电，同时信号驱动器连接到第二控制线，并且将信号驱动器与第二控制线断开。对控制线进行充电导致相应的非易失性存储元件经历程序操作。在不等待第一非易失性存储元件的程序操作完成的情况下，执行信号驱动器与第一控制线的断开，将信号驱动器连接到第二控制线和第二控制线的充电。

8. 发明申请

US20100265750A1 MEMORY SYSTEM WITH DATA LINE SWITCHING SCHEME 有权
标题翻译：具有数据线切换方案的存储器系统
公开(公告)号：US20100265750A1
公开(公告)日：2010-10-21
申请号：US12563139
申请日：2009-09-20
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02 , G11C11/00 , G11C5/06
CPC分类号： G11C8/12 , G11C13/0064 , G11C13/0069 , G11C2013/0066
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selections circuits can change their selections independently of each other. For example, a memory operation is performed concurrently on a first non-volatile storage element of each group of a plurality of groups of non-volatile storage elements. Completion of the memory operation for the first non-volatile storage element of each group is independently detected. A memory operation on a second non-volatile storage element of each group is independently commenced for each group upon independently detecting completion of the memory operation for the first non-volatile storage element of the respective group.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。每个块包括用于选择性地将第一类型的阵列线（例如位线）的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到连接到控制电路的全局数据线的第二选择电路的子集。为了提高存储器操作的性能，第二选择电路可以彼此独立地改变它们的选择。例如，在多组非易失性存储元件的每组的第一非易失性存储元件上同时执行存储器操作。独立检测每组的第一非易失性存储元件的存储器操作的完成。在独立地检测对相应组的第一非易失性存储元件的存储器操作的完成时，对于每个组，在每个组的第二非易失性存储元件上的存储器操作被独立地开始。

9. 发明授权

US08982597B2 Memory system with sectional data lines 有权
标题翻译：具有分段数据线的存储器系统
公开(公告)号：US08982597B2
公开(公告)日：2015-03-17
申请号：US13362320
申请日：2012-01-31
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02 , G11C16/24 , G11C13/00
CPC分类号： G11C16/24 , G11C13/0028
摘要： The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
摘要翻译：该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。每个一个或多个块的集合包括一组本地数据线。每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

10. 发明授权

US08279650B2 Memory system with data line switching scheme 有权
标题翻译：具有数据线切换方案的存储系统
公开(公告)号：US08279650B2
公开(公告)日：2012-10-02
申请号：US12563139
申请日：2009-09-20
申请人： Tianhong Yan , Luca Fasoli
发明人： Tianhong Yan , Luca Fasoli
IPC分类号： G11C5/02 , G11C11/00 , G11C5/06
CPC分类号： G11C8/12 , G11C13/0064 , G11C13/0069 , G11C2013/0066
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selections circuits can change their selections independently of each other. For example, a memory operation is performed concurrently on a first non-volatile storage element of each group of a plurality of groups of non-volatile storage elements. Completion of the memory operation for the first non-volatile storage element of each group is independently detected. A memory operation on a second non-volatile storage element of each group is independently commenced for each group upon independently detecting completion of the memory operation for the first non-volatile storage element of the respective group.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。每个块包括用于选择性地将第一类型的阵列线（例如位线）的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到连接到控制电路的全局数据线的第二选择电路的子集。为了提高存储器操作的性能，第二选择电路可以彼此独立地改变它们的选择。例如，在多组非易失性存储元件的每组的第一非易失性存储元件上同时执行存储器操作。独立检测每组的第一非易失性存储元件的存储器操作的完成。在独立地检测对相应组的第一非易失性存储元件的存储器操作的完成时，对于每个组，在每个组的第二非易失性存储元件上的存储器操作被独立地开始。

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