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1. 再颁专利

USRE39385E1 Method and apparatus for performing mathematical functions using polynomial approximation and a rectangular aspect ratio multiplier 失效
标题翻译：使用多项式近似和矩形长宽比乘数执行数学函数的方法和装置
公开(公告)号：USRE39385E1
公开(公告)日：2006-11-07
申请号：US08109577
申请日：1993-08-19
申请人： Thomas B. Brightman , Willard S. Briggs , Warren E. Ferguson
发明人： Thomas B. Brightman , Willard S. Briggs , Warren E. Ferguson
IPC分类号： G06F7/52
CPC分类号： G06F7/544
摘要： A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system (10) which comprises a control and timing circuit (18), a microprogram store (20) and a multiplier circuit (34). The multiplier circuit (34) may comprise a rectangular aspect ratio multiplier circuit (40) having an additional ADDER INPUT to enable the repeated evaluation of first order polynomials to evaluate polynomial expansions associated with each mathematical function. A constant store (28) is used to store predetermined coefficients for the polynomial expansion associated with each mathematical functions function. The microprogram store (20) is used to store argument transformation routines, polynomial expansions and result transformation routines associated with each mathematical function. The questions raised in reexamination request No. 90/004,138, filed Feb. 12, 1996, have been considered and the results thereof are reflected in this reissue patent which constitutes the reexamination certificate required by 35 U.S.C. 307 as provided in 37 CFR 1.570(e).
摘要翻译：在包括控制和定时电路（18），微程序存储（20）和乘法器电路（34）的数字处理系统（10）中实现用于使用多项式扩展近似数学函数的方法。乘法器电路（34）可以包括具有额外的ADDER INPUT的矩形宽高比乘法器电路（40），以使得能够重复评估一阶多项式以评估与每个数学函数相关联的多项式扩展。常数存储器（28）用于存储与每个数学相关联的多项式展开的预定系数<？delete-start id =“DEL-S-00001”date =“20061107”？>函数<？delete-end id =“ DEL-S-00001“？> <？insert-start id =”INS-S-00001“date =”20061107“？> function <？insert-end id =”INS-S-00001“？>。微程序存储器（20）用于存储与每个数学函数相关联的参数转换程序，多项式展开和结果转换程序。已经考虑了1996年2月12日提交的第90 / 004,138号复审请求中提出的问题，其结果反映在该重新颁发专利中，该专利构成了35U.S.C.所要求的复审证书。 307如第37 CFR 1.570（e）条所规定。

2. 发明授权

US5060182A Method and apparatus for performing the square root function using a rectangular aspect ratio multiplier 失效
标题翻译：使用矩形纵坐标乘法器执行平方根功能的方法和装置
公开(公告)号：US5060182A
公开(公告)日：1991-10-22
申请号：US402822
申请日：1989-09-05
申请人： Willard S. Briggs , Thomas B. Brightman , David W. Matula
发明人： Willard S. Briggs , Thomas B. Brightman , David W. Matula
IPC分类号： G06F7/552
CPC分类号： G06F7/5525
摘要： A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal. The root digit value is squared and the exact square is subtracted from the operand to yield an exact remainder. Succeeding new root digit values are determined by multiplying the short reciprocal by the appropriately shifted current remainder, selectively adding a digit bias adjustment factor and truncating the product. The root digit values are appropriately shifted and accumulated to form a partial root. The described steps are repeated to serially generate root digit values and partial roots with corresponding new exact remainders.

3. 发明授权

US5159566A Method and apparatus for performing the square root function using a rectangular aspect ratio multiplier 失效
标题翻译：使用矩形宽高比乘数执行平方根函数的方法和装置
公开(公告)号：US5159566A
公开(公告)日：1992-10-27
申请号：US852917
申请日：1992-03-13
申请人： Willard S. Briggs , Thomas B. Brightman , David W. Matula
发明人： Willard S. Briggs , Thomas B. Brightman , David W. Matula
IPC分类号： G06F7/552
CPC分类号： G06F7/5525
摘要： A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect raio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal. The root digit value is squared and the exact square is subtracted from the operand to yield an exact remainder. Succeeding new root digit values are determined by multiplying the short reciprocal by the appropriately shifted current remainder, selectively adding a digit bias adjustment factor and truncating the product. The root digit values are appropriately shifted and accumulated to form a partial root. The described steps are repeated to serially generate root digit values and partial roots with corresponding new exact remainders.
摘要翻译：一种用于执行平方根函数的方法和装置，其首先包括近似操作数的平方根的短倒数。将相应的偏差调整因子添加到近似值中，并将结果截断以形成正确偏置的短倒数。然后将该短互逆乘以操作数的预定数量的最高有效位，并且将产品适当地截断以产生第一根数值。乘法发生在具有矩形方面的乘法器阵列中，其中长边具有基本上与期望的全精度根所需的位数一样大的位数。乘法器阵列的短边比单个根数值所需的位数多几个保护位的位数稍大一些，这也被确定为短倒数中的位数。根数值平方，并从操作数中减去精确的平方，以产生精确的余数。通过将短倒数乘以适当移位的电流余数来确定新的根数值，选择性地添加数字偏差调整因子并截断产品。根数值被适当地移位和累加以形成部分根。重复描述的步骤以连续地产生具有相应新的精确余数的根数值和部分根。

4. 发明授权

US4626985A Single-chip microcomputer with internal time-multiplexed address/data/interrupt bus 失效
标题翻译：具有内部时间复用地址/数据/中断总线的单片机
公开(公告)号：US4626985A
公开(公告)日：1986-12-02
申请号：US783261
申请日：1985-10-03
申请人： Willard S. Briggs
发明人： Willard S. Briggs
IPC分类号： G06F13/24 , G06F15/78 , G06F13/40
CPC分类号： G06F13/24 , G06F15/7814
摘要： A microcomputer architecture permits communication between a CPU and same-chip ports and input/output circuits to be carried only over a multiplexed address/data/interrupt bus, thereby permitting modified I/O hardware or other circuits to be included in the microcomputer without disturbing the CPU layout.
摘要翻译：微机架构允许CPU和相同芯片端口之间的通信和输入/输出电路仅通过多路复用的地址/数据/中断总线承载，从而允许修改的I / O硬件或其他电路被包括在微型计算机中而不会干扰 CPU布局。

5. 发明授权

US5801720A Data transfer from a graphics subsystem to system memory 失效
标题翻译：从图形子系统到系统内存的数据传输
公开(公告)号：US5801720A
公开(公告)日：1998-09-01
申请号：US604008
申请日：1996-02-20
申请人： Forrest E. Norrod , Willard S. Briggs , Christopher G. Wilcox , Brian D. Falardeau , Sameer Y. Nanavati
发明人： Forrest E. Norrod , Willard S. Briggs , Christopher G. Wilcox , Brian D. Falardeau , Sameer Y. Nanavati
IPC分类号： G06F3/14 , G09G5/393 , G06F13/00
CPC分类号： G09G5/393 , G06F3/14 , G09G2360/125
摘要： A processing system includes a graphics subsystem that directly renders raster data to system memory and moves bitmaps between locations within system memory with the graphics subsystem providing the data and a processor providing the virtual-to-physical addresses with privilege and protection check mechanisms.
摘要翻译：处理系统包括图形子系统，其直接将光栅数据呈现给系统存储器并且利用提供数据的图形子系统和处理器为虚拟到物理地址提供特权和保护检查机制来移动系统存储器内的位置之间的位图。

6. 发明授权

US5144576A Signed digit multiplier 失效
标题翻译：签名数字乘法器
公开(公告)号：US5144576A
公开(公告)日：1992-09-01
申请号：US402798
申请日：1989-09-05
申请人： Willard S. Briggs , David W. Matula
发明人： Willard S. Briggs , David W. Matula
IPC分类号： G06F7/52 , G06F7/48 , G06F7/506 , G06F7/53 , G06F7/533 , G06F7/535 , G06F7/552
CPC分类号： G06F7/4824
摘要： A rectangular array signed digit multiplier circuit (10) is disclosed which comprises a multiplier core (28). The circuit (10) comprises a C-latch (14), a D-latch (18), an A-latch (26), and a feedback latch (52) operable to store operands to be input into the multiplier core (28) through a MULTIPLIER INPUT, a multiplicand INPUT, and ADDER INPUT and a FEEDBACK INPUT, respectively, The product output by the multiplier core (28) may comprise the sum of the product of the values input through the MULTIPLIER INPUT and MULTIPLICAND INPUT and the ADDER and FEEDBACK INPUTS. The product is stored in a result latch (40) and may be used in subsequent passes through multiplier core (28) through the use of a data path coupling result latch (40) with feedback latch (52). Multiplier core (28) comprises a series connection of a times three adder level (56), a Booth recoder level (58), a partial product generator level (60), a level one adder level (62), a level two adder level (64) and a level three adder level (66).

7. 发明授权

US4649471A Address-controlled automatic bus arbitration and address modification 失效
标题翻译：地址控制自动总线仲裁和地址修改
公开(公告)号：US4649471A
公开(公告)日：1987-03-10
申请号：US471095
申请日：1983-03-01
申请人： Willard S. Briggs , Alan D. Gant , Parveen K. Gupta , Isadore S. Ferson
发明人： Willard S. Briggs , Alan D. Gant , Parveen K. Gupta , Isadore S. Ferson
IPC分类号： G06F13/16 , G06F12/06 , G06F13/362 , G06F15/78 , G06F13/18
CPC分类号： G06F12/0653 , G06F13/362
摘要： A microcomputer includes I/O ports and registers which are mapped in memory space along with RAM and ROM and in which hardware invisible to the programmer performs a bus arbitration sequence to acquire an external bus when an off-chip reference requires the bus; and in which memory space that is used for on-chip references is recovered for use in external memory by manipulating bits in the memory address.
摘要翻译：微型计算机包括与RAM和ROM一起映射到存储器空间中的I / O端口和寄存器，并且当片外参考需要总线时，编程器不可见的硬件执行总线仲裁序列以获取外部总线; 并且其中用于片上引用的存储器空间通过操纵存储器地址中的位而被恢复用于外部存储器。

8. 发明授权

US4451885A Bit operation method and circuit for microcomputer 失效
标题翻译：微机的位操作方法和电路
公开(公告)号：US4451885A
公开(公告)日：1984-05-29
申请号：US353602
申请日：1982-03-01
申请人： Isadore S. Gerson , Willard S. Briggs
发明人： Isadore S. Gerson , Willard S. Briggs
IPC分类号： G06F9/308 , G06F7/00
CPC分类号： G06F9/30018
摘要： A microcomputer circuit is described for carrying out bit operations between registers and ports without the need for bit testing followed by branch operations. The microcomputer includes a bus (10) connected to provide communication to an ALU (22), registers (11, 12) and a serial port (13). A bit test circuit is connected to the bus (10) and provides a selected bit to a temporary carry storage (18) which in turn transfers the selected bit to a carry flag location (28a) within a status register (28). Instruction codes are input to an instruction register (32) which provides operating commands to an entry ROM (36) and an ALU control circuit (40). After a bit test operation is completed and in response to a copy or exchange instruction provided to the instruction register (32) a bit can be copied from one register to another register, bits can be exchanged between two registers or bits within a register can be parallel-to-serial converted and provided to the serial port (13). Each of these operations is carried out without the need for employing branch operations following the test of a bit. The present invention provides dynamic bit operations without the need for testing the state of a bit to determine conditional branching for selecting set or clear operations. With the present invention the speed of bit operations is improved and the amount of code stored in program memory can be reduced.
摘要翻译：描述了一种用于在寄存器和端口之间执行位操作的微计算机电路，而不需要进行位测试，随后进行分支操作。微型计算机包括连接到ALU（22），寄存器（11,12）和串行端口（13）的通信的总线（10）。位测试电路连接到总线（10），并将所选择的位提供给临时进位存储器（18），临时进位存储器又将所选择的位传送到状态寄存器（28）内的进位标志位置（28a）。指令代码被输入到向条目ROM（36）和ALU控制电路（40）提供操作命令的指令寄存器（32）。在完成了一个测试操作并且响应于提供给指令寄存器（32）的复制或交换指令之后，可以将一个位从一个寄存器复制到另一个寄存器，可以在两个寄存器之间交换位，寄存器中的位可以是并行转换并提供给串行端口（13）。执行这些操作中的每一个，而不需要在经过一点测试之后采用分支操作。本发明提供动态位操作，而不需要测试位的状态来确定用于选择设置或清除操作的条件分支。利用本发明，提高了位操作的速度，并且可以减少存储在程序存储器中的代码量。

9. 发明授权

US5307303A Method and apparatus for performing division using a rectangular aspect ratio multiplier 失效
标题翻译：使用矩形宽高比乘数进行分割的方法和装置
公开(公告)号：US5307303A
公开(公告)日：1994-04-26
申请号：US810710
申请日：1991-12-18
申请人： Willard S. Briggs , David W. Matula
发明人： Willard S. Briggs , David W. Matula
IPC分类号： G06F7/491 , G06F7/52
CPC分类号： G06F7/4917 , G06F7/535 , G06F7/5375 , G06F2207/5351 , G06F2207/5355
摘要： A method and apparatus for performing division is described which first comprises approximating the short reciprocal of the divisor. A reciprocal bias adjustment factor is added to the approximation and the correctly biased short reciprocal is multiplied by a predetermined number of the most significant bits of the dividend and the product is truncated to generate a first quotient digit value. The multiplication takes place in a multiplier array having a rectangular aspect ratio with the long side having a number of bits at least as large as the number of bits required for the divisor. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single quotient digit value, which is also determined to be the number of bits in the short reciprocal. The quotient digit value is multiplied by the full divisor and the exact product is subtracted from the dividend to yield an exact partial remainder. The described steps are repeated to serially generate quotient digit values with exact partial remainders with the preceding partial remainder taking the place of the dividend. The quotient digit values are accumulated to yield a complete quotient. The complete quotient is decremented and the remainder recalculated if the final partial remainder is negative, yield the full precision unique quotient and non-negative remainder pair.
摘要翻译：描述了用于执行划分的方法和装置，其首先包括近似除数的短倒数。将相应的偏置调整因子加到近似值中，并将正确偏置的短互逆乘以被除数的预定数量的最高有效位，并且产品被截断以产生第一商数位值。乘法发生在具有矩形长宽比的乘法器阵列中，长边具有至少与除数所需的比特数一样大的比特数。乘法器阵列的短边具有比单个商数值所需的位数多几个保护位的位数，其也被确定为短倒数中的位数。商数值乘以完全除数，并从分红中减去确切产品，以产生精确的部分余数。重复描述的步骤以用精确的部分余数串行地生成商数值，其中前面的部分余数取代了除数。商数值被累积以产生一个完整的商。如果最终的部分余数为负，则完整商减少，剩余部分重新计算，产生全精度唯一商和非负余数对。

10. 发明授权

US5184318A Rectangular array signed digit multiplier 失效
标题翻译：矩形数组有符号位乘数
公开(公告)号：US5184318A
公开(公告)日：1993-02-02
申请号：US813942
申请日：1991-12-24
申请人： Willard S. Briggs , David W. Matula
发明人： Willard S. Briggs , David W. Matula
IPC分类号： G06F7/48
CPC分类号： G06F7/4824
摘要： A rectangular array signed digit multiplier circuit 10 is disclosed which comprises a multiplier core (28). The circuit (10) comprises a C-latch (14), a D-latch (18), and A-latch (26), and a feedback latch (52) operable to store operands to be input into the multiplier core (28) through a MULTIPLIER INPUT, a multiplicand INPUT, an ADDER INPUT and a FEEDBACK INPUT, respectively. The product output by the multiplier core (28) may comprise the sum of the product of the values input through the MULTIPLIER INPUT and MULTIPLICAND INPUT and the ADDER and FEEDBACK INPUTS. The product is stored in a result latch (40) and may be used in subsequent passes through multiplier core (28) through the use of a data path coupling result latch (40) with feedback latch (52). Multiplier core (28) comprises a series connection of a times three adder level (56), a Booth recoder level (58), a partial product generator level (60), a level one adder level (62), a level two adder level (64) and a level three adder level (66).
摘要翻译：公开了一种矩阵阵列有符号数乘法器电路10，其包括乘法器芯（28）。电路（10）包括C锁存器（14），D锁存器（18）和A锁存器（26），反馈锁存器（52）可操作以存储要输入到乘法器内核（28）的操作数）分别通过MULTIPLIER INPUT，被乘数输入，ADDER INPUT和FEEDBACK INPUT输入。由乘法器芯（28）输出的乘积可以包括通过MULTIPLIER INPUT和MULTIPLICAND INPUT输入的值与ADDER和FEEDBACK INPUTS的乘积之和。产品被存储在结果锁存器（40）中，并且可以在通过使用具有反馈锁存器（52）的数据通路耦合结果锁存器（40）的后续通过乘法器内核（28）中使用。乘法器核心（28）包括三次加法器电平（56），布朗编码器电平（58），部分乘积发生器电平（60），一级加法器电平（62），二级加法器电平（64）和三级加法器级（66）。

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