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    • 3. 发明申请
    • EXHAUST GAS PURIFICATION SYSTEM IN UPLAND AREA
    • 内陆地区排气净化系统
    • US20130061582A1
    • 2013-03-14
    • US13699503
    • 2011-05-16
    • Takashi IkedaTakayuki MukunashiTetsuya Asami
    • Takashi IkedaTakayuki MukunashiTetsuya Asami
    • F01N3/023
    • F01N3/023F01N3/0235F01N3/035F01N9/002F02D41/0245F02D41/029F02D41/405F02D2200/101F02D2200/703Y02T10/26Y02T10/44
    • When a diesel particulate diffuser (“DPD”) of a vehicle traveling in a normal drive mode in the upland area is to be automatically regenerated by raising a temperature of exhaust gas from an engine, an exhaust gas purification system determines an upland full-load injection quantity from the atmospheric pressure in the upland area and an engine speed while the vehicle is in motion and drives the vehicle with the injection quantity determined. The system determines, during the regeneration mode, an upland drive regeneration injection quantity obtained by decreasing the upland full-load injection quantity on the basis of a quantity required for the post-injection. The injection quantity is gradually decreased from the upland full-load injection quantity to the upland regeneration drive injection quantity when the vehicle shifts from the normal drive mode in the upland area to the upland regeneration mode, so that the decreased quantity is used for the post-injection.
    • 当通过提高发动机的排气温度来自动再生在高地区以正常的行驶模式行驶的车辆的柴油颗粒物扩散器(DPD)时,废气净化系统确定高地全负荷喷射量 从高空地区的大气压力和车辆运动时的发动机转速,并以确定的喷射量驱动车辆。 该系统在再生模式期间确定通过基于后喷射所需的量减少高地满载喷射量而获得的高地驱动再生喷射量。 当车辆从高原地区的正常行驶模式转移到高地再生模式时,喷射量从高地满载喷射量逐渐降低到高地再生驱动喷射量,使用量减少 -注射。
    • 4. 发明授权
    • Semiconductor integrated circuit device, method of estimating failure ratio of such devices on the market, and method of manufacturing the devices
    • 半导体集成电路器件,市场上这种器件的故障率的估计方法以及器件的制造方法
    • US06223097B1
    • 2001-04-24
    • US09265876
    • 1999-03-11
    • Takehiro HashimotoYutaka TanakaTetsuya AsamiYouichi SatouNoriaki Okumiya
    • Takehiro HashimotoYutaka TanakaTetsuya AsamiYouichi SatouNoriaki Okumiya
    • B07C1700
    • H01L22/20H01L2924/0002H01L2924/00
    • In a method for setting appropriate initial-failure screening conditions when mass-producing semiconductor devices of multiple types, devices of each type being manufactured in a small number, the step of subjecting products of every type to an acceleration test is excluded, and instead, the failure ratio on the market of semiconductor devices of each type is estimated using a testing semiconductor device. Specifically, {circle around (1)} first, all types of semiconductor devices to be developed and mass-produced are classified into several groups. {circle around (2)} A test semiconductor device is developed which has the same number of elements, the same gate area, the same multi-layer wiring length and the same number of contact holes as the average number of elements, the average gate area, the average wiring length and the average number of contact holes of the semiconductor devices included in one of the type groups, respectively. The testing semiconductor device has main features (design rules, MOSFET structure, wiring structure, etc.) common to the types included in its corresponding type group, and a failed portion thereof, if any, can be easily detected by an analysis using a tester.
    • 在批量生产多种类型的半导体器件的情况下设置适当的初始故障筛选条件的方法中,每种类型的器件被少量制造,不考虑每种类型的产品进行加速度测试的步骤, 使用测试半导体器件来估计每种类型的半导体器件市场的故障率。 具体来说,首先,围绕(1)圆)将要开发和批量生产的所有类型的半导体器件分为几组。 {circle around(2)}开发了一种测试半导体器件,其具有与元件的平均数目相同数量的元件,相同的栅极面积,相同的多层布线长度和相同数量的接触孔,平均栅极 面积,平均布线长度和包括在一个类型组中的半导体器件的接触孔的平均数量。 测试半导体器件具有与其对应类型组中包括的类型相同的主要特征(设计规则,MOSFET结构,布线结构等),并且其故障部分(如果有的话)可以通过使用测试仪的分析容易地检测 。
    • 6. 发明授权
    • SRAM-based semiconductor integrated circuit testing element
    • 基于SRAM的半导体集成电路测试元件
    • US06445002B1
    • 2002-09-03
    • US09621452
    • 2000-07-21
    • Takehiro HashimotoYutaka TanakaTetsuya AsamiYouichi SatouNoriaki Okumiya
    • Takehiro HashimotoYutaka TanakaTetsuya AsamiYouichi SatouNoriaki Okumiya
    • H01L2358
    • H01L22/20H01L2924/0002H01L2924/00
    • In a method for setting appropriate initial-failure screening conditions when mass-producing semiconductor devices of multiple types, devices of each type being manufactured in a small number, the step of subjecting products of every type to an acceleration test is excluded, and instead, the failure ratio on the market of semiconductor devices of each type is estimated using a testing semiconductor device. Specifically, {circle around (1)} first, all types of semiconductor devices to be developed and mass-produced are classified into several groups. {circle around (2)} A test semiconductor device is developed which has the same number of elements, the same gate area, the same multi-layer wiring length and the same number of contact holes as the average number of elements, the average gate area, the average wiring length and the average number of contact holes of the semiconductor devices included in one of the type groups, respectively. The testing semiconductor device has main features (design rules, MOSFET structure, wiring structure, etc.) common to the types included in its corresponding type group, and a failed portion thereof, if any, can be easily detected by an analysis using a tester.
    • 在批量生产多种类型的半导体器件的情况下设置适当的初始故障筛选条件的方法中,每种类型的器件被少量制造,不考虑每种类型的产品进行加速度测试的步骤, 使用测试半导体器件来估计每种类型的半导体器件市场的故障率。 具体来说,首先,围绕(1)圆)将要开发和批量生产的所有类型的半导体器件分为几组。 {circle around(2)}开发了一种测试半导体器件,其具有与元件的平均数目相同数量的元件,相同的栅极面积,相同的多层布线长度和相同数量的接触孔,平均栅极 面积,平均布线长度和包括在一个类型组中的半导体器件的接触孔的平均数量。 测试半导体器件具有与其对应类型组中包括的类型相同的主要特征(设计规则,MOSFET结构,布线结构等),并且其故障部分(如果有的话)可以通过使用测试仪的分析容易地检测 。
    • 7. 发明授权
    • Method for forming contact portion in semiconductor integrated circuit
devices
    • 在半导体集成电路器件中形成接触部分的方法
    • US4800176A
    • 1989-01-24
    • US183138
    • 1988-04-19
    • Masakazu KakumuTetsuya Asami
    • Masakazu KakumuTetsuya Asami
    • H01L21/3205H01L21/768H01L21/283
    • H01L21/76819H01L21/76877
    • A method of manufacturing semiconductor devices according to the present invention includes the steps of forming an element isolation region on the main surface of a semiconductor substrate of a first conductivity type, forming a high impurity concentration layer of a second conductivity type in the surface area of a portion of the semiconductor substrate defined by the element isolation region, and forming a first insulation film on the entire surface of the resultant semiconductor structure. Thereafter, a contact hole is formed in the first insulation film which is formed on the high impurity concentration layer, a semiconductor layer containing an impurity of the same conductivity type as the high impurity concentration layer is formed on the first insulation film, and a second insulation film is formed on the semiconductor layer. After this, a planarization film is formed on the entire surface of the second insulation film and is then selectively removed by anisotropic etching, to leave part of the planarization film filling the contact hole. Then, the portion of the planarization film exposed by the anisotropic etching is removed, a metal layer is formed on the entire surface of the resultant semiconductor structure, and the metal layer and semiconductor layer are patterned to form a laminated structure of a wiring layer.
    • 根据本发明的制造半导体器件的方法包括以下步骤:在第一导电类型的半导体衬底的主表面上形成元件隔离区,在第二导电类型的半导体衬底的表面积中形成第二导电类型的高杂质浓度层 由所述元件隔离区限定的所述半导体衬底的一部分,以及在所得半导体结构的整个表面上形成第一绝缘膜。 此后,在形成在高杂质浓度层上的第一绝缘膜中形成接触孔,在第一绝缘膜上形成含有与高杂质浓度层相同的导电类型的杂质的半导体层, 在半导体层上形成绝缘膜。 之后,在第二绝缘膜的整个表面上形成平坦化膜,然后通过各向异性蚀刻选择性地去除平坦化膜,以使部分平坦化膜填充接触孔。 然后,除去通过各向异性蚀刻曝光的平坦化膜的部分,在所得半导体结构的整个表面上形成金属层,并对金属层和半导体层进行构图以形成布线层的层叠结构。