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1. 发明授权

US06334199B1 Method of generating test patterns for a logic circuit, a system performing the method, and a computer readable medium instructing the system to perform the method 失效
标题翻译：生成逻辑电路的测试模式的方法，执行该方法的系统以及指示系统执行该方法的计算机可读介质
公开(公告)号：US06334199B1
公开(公告)日：2001-12-25
申请号：US09236903
申请日：1999-01-26
申请人： Toshinobu Ono , Tamaki Toumiya
发明人： Toshinobu Ono , Tamaki Toumiya
IPC分类号： G01R3128
CPC分类号： G01R31/318321
摘要： In a method of test pattern generation for logic circuits, a whole circuit is divided into a plurality of partial circuits for test pattern generation by distributed-processing. ATG (Algorithmic Test Generation) process is performed per each of the partial circuits based on the result of RTG (Random Test Generation) process. Also disclosed are a test pattern generation system performing the method, and computer readable media having program for the test pattern generation system to perform the method.
摘要翻译：在逻辑电路的测试图形生成方法中，通过分布式处理将整个电路划分成用于测试图形生成的多个部分电路。基于RTG（随机测试生成）处理的结果，每个部分电路执行ATG（算法测试生成）处理。还公开了执行该方法的测试模式生成系统，以及具有用于测试模式生成系统执行该方法的程序的计算机可读介质。

2. 发明授权

US5502730A Partial scan testability utilizing reconvergence through sequential elements 失效
标题翻译：通过顺序元素利用重新收敛的部分扫描可测性
公开(公告)号：US5502730A
公开(公告)日：1996-03-26
申请号：US258585
申请日：1994-06-10
申请人： Rabindra K. Roy , Toshinobu Ono
发明人： Rabindra K. Roy , Toshinobu Ono
IPC分类号： G01R31/28 , G01R31/3185 , H04B17/00
CPC分类号： G01R31/318586
摘要： A method of selecting circuit elements in a sequential circuit for partial scan testing relies upon analyzing and breaking reconvergence through the selected circuit element. Different types of reconvergences present in the circuit and their affect on the circuit testability are considered. Harmful reconvergence present in the circuit are broken by scanning a memory element present in the reconvergence path.
摘要翻译：在用于部分扫描测试的顺序电路中选择电路元件的方法依赖于通过所选择的电路元件分析和断开再聚合。考虑电路中存在的不同类型的再现，以及它们对电路可测性的影响。存在于电路中的有害再聚合通过扫描存在于再会聚路径中的存储元件而被破坏。

3. 发明授权

US08441277B2 Semiconductor testing device, semiconductor device, and testing method 失效
标题翻译：半导体测试装置，半导体器件和测试方法
公开(公告)号：US08441277B2
公开(公告)日：2013-05-14
申请号：US12810877
申请日：2008-12-16
申请人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
发明人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
IPC分类号： G01R31/26
CPC分类号： G01R31/31908
摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.
摘要翻译：提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。

4. 发明申请

US20100283497A1 SEMICONDUCTOR TESTING DEVICE, SEMICONDUCTOR DEVICE, AND TESTING METHOD 失效
标题翻译：半导体测试器件，半导体器件和测试方法
公开(公告)号：US20100283497A1
公开(公告)日：2010-11-11
申请号：US12810877
申请日：2008-12-16
申请人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
发明人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
IPC分类号： G01R31/26
CPC分类号： G01R31/31908
摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.
摘要翻译：提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。

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