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1. 发明申请

US20120119342A1 ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：先进的四边平面非引线封装结构及其制造方法
公开(公告)号：US20120119342A1
公开(公告)日：2012-05-17
申请号：US12944695
申请日：2010-11-11
申请人： Pao-Huei Chang Chien , Ping-Cheng Hu , Po-Shing Chiang , Wei-Lun Cheng , Hsueh-Te Wang , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Ping-Feng Yang
发明人： Pao-Huei Chang Chien , Ping-Cheng Hu , Po-Shing Chiang , Wei-Lun Cheng , Hsueh-Te Wang , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Ping-Feng Yang
IPC分类号： H01L23/495 , H01L21/58 , H01L21/56
CPC分类号： H01L21/4832 , H01L21/561 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/4911 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound.
摘要翻译：先进的四边形扁平无铅封装结构包括载体，芯片，多根导线和模塑料。载体包括管芯焊盘和多个引线。引线的内引线被设计成具有弯曲的侧壁，用于增强内引线和周围模塑料之间的粘附。

2. 发明申请

US20120091575A1 Semiconductor Package And Method For Making The Same 审中-公开
标题翻译：半导体封装及其制作方法
公开(公告)号：US20120091575A1
公开(公告)日：2012-04-19
申请号：US12905756
申请日：2010-10-15
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L23/48 , H01L24/02 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L2224/02371 , H01L2224/02381 , H01L2224/0401 , H01L2224/14155 , H01L2224/16225 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/32105 , H01L2224/32145 , H01L2224/32225 , H01L2224/33183 , H01L2224/73103 , H01L2224/73203 , H01L2224/81191 , H01L2224/83192 , H01L2224/83815 , H01L2224/83851 , H01L2224/83903 , H01L2225/06517 , H01L2225/06531 , H01L2225/06551 , H01L2225/06555 , H01L2924/014 , H01L2924/00012
摘要： The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, at least one first chip, a dielectric layer and at least one second chip. The first chip is attached and electrically connected to the substrate. The first chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The dielectric layer is disposed on the first active surface. The second chip is attached and electrically connected to the substrate by metal bumps. The second chip includes a second active surface and a plurality of second signal coupling pads. The second active surface contacts the dielectric layer. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap between the first signal coupling pads of the first chip and the second signal coupling pads of the second chip is controlled by the thickness of the dielectric layer. Therefore, the mass-production yield of the semiconductor package is increased.
摘要翻译：半导体封装及其制造方法技术领域本发明涉及半导体封装及其制造方法。半导体封装包括衬底，至少一个第一芯片，电介质层和至少一个第二芯片。第一芯片被附接并电连接到基板。第一芯片包括第一有源表面和多个第一信号耦合焊盘。第一信号耦合焊盘设置成与第一有源表面相邻。电介质层设置在第一有源表面上。第二芯片通过金属凸块附接和电连接到基板。第二芯片包括第二有源表面和多个第二信号耦合焊盘。第二活性表面接触电介质层。第二信号耦合焊盘设置成与第二有源表面相邻，并且电容耦合到第一芯片的第一信号耦合焊盘，以便提供第一芯片和第二芯片之间的接近通信。由此，第一芯片的第一信号耦合焊盘与第二芯片的第二信号耦合焊盘之间的间隙由电介质层的厚度来控制。因此，半导体封装的批量生产量增加。

3. 发明申请

US20120049360A1 Semiconductor Package And Method For Making The Same 有权
标题翻译：半导体封装及其制作方法
公开(公告)号：US20120049360A1
公开(公告)日：2012-03-01
申请号：US12872644
申请日：2010-08-31
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
IPC分类号： H01L23/538 , H01L21/60
CPC分类号： H01L21/6835 , H01L21/563 , H01L21/568 , H01L23/3114 , H01L24/27 , H01L25/0652 , H01L25/50 , H01L2224/1184 , H01L2224/131 , H01L2224/1329 , H01L2224/16145 , H01L2224/2784 , H01L2224/73104 , H01L2224/73204 , H01L2224/81005 , H01L2224/81801 , H01L2224/8185 , H01L2224/831 , H01L2225/06513 , H01L2924/15311 , H01L2924/15321 , H01L2924/014
摘要： The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The first metal bumps are disposed on the first active surface of the first layer chip. The second layer chip is electrically connected to the first layer chip, and includes a second active surface and a plurality of second signal coupling pads. The second active surface faces the first active surface of the first layer chip. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first layer chip, so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps and the second layer chip, and the first metal bumps are partially exposed. Whereby, the bonding strength between the first layer chip and the second layer chip is increased because of the package body, so the yield of the semiconductor package is increased.
摘要翻译：半导体封装及其制造方法技术领域本发明涉及半导体封装及其制造方法。半导体封装包括至少一个第一层芯片，多个第一金属凸块，至少一个第二层芯片和封装体。第一层芯片包括第一有源表面和多个第一信号耦合焊盘。第一信号耦合焊盘设置成与第一有源表面相邻。第一金属凸块设置在第一层芯片的第一有源表面上。第二层芯片电连接到第一层芯片，并且包括第二有源表面和多个第二信号耦合焊盘。第二活性表面面向第一层芯片的第一活性表面。第二信号耦合焊盘设置成与第二有源表面相邻，并且电容耦合到第一层芯片的第一信号耦合焊盘，以便提供第一层芯片和第二层芯片之间的邻近通信。封装体封装第一层芯片，第一金属凸块和第二层芯片，并且第一金属凸块部分地露出。因此，由于封装体，第一层芯片和第二层芯片之间的结合强度增加，所以半导体封装的产量增加。

4. 发明授权

US08076786B2 Semiconductor package and method for packaging a semiconductor package 有权
标题翻译：用于封装半导体封装的半导体封装和方法
公开(公告)号：US08076786B2
公开(公告)日：2011-12-13
申请号：US12501693
申请日：2009-07-13
申请人： Chang Ying Hung , Hsiao Chuan Chang , Tsung Yueh Tsai , Yi Shao Lai , Jian Cheng Chen , Wei Chi Yih , Ho Ming Tong
发明人： Chang Ying Hung , Hsiao Chuan Chang , Tsung Yueh Tsai , Yi Shao Lai , Jian Cheng Chen , Wei Chi Yih , Ho Ming Tong
IPC分类号： H01L23/488
CPC分类号： H01L24/85 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05552 , H01L2224/05554 , H01L2224/05555 , H01L2224/05624 , H01L2224/05647 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48624 , H01L2224/48647 , H01L2224/48824 , H01L2224/48847 , H01L2224/73265 , H01L2224/78301 , H01L2224/85043 , H01L2224/85045 , H01L2224/85201 , H01L2224/92247 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.
摘要翻译：引线键合结构包括芯片和接合线。芯片包括基材，至少一个第一金属垫，再分布层和至少一个第二金属垫。第一金属垫设置在基材上。再分布层具有第一端和第二端，并且第一端电连接到第一金属垫。第二金属垫电连接到再分配层的第二端。接合线接合到第二金属垫。

5. 发明授权

US08072064B1 Semiconductor package and method for making the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US08072064B1
公开(公告)日：2011-12-06
申请号：US12819796
申请日：2010-06-21
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
IPC分类号： H01L21/00
CPC分类号： H01L23/48 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/06513 , H01L2225/06531 , H01L2225/06541 , H01L2924/00014 , H01L2924/1815 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance. The third signal coupling pads are disposed on the second non-top metal layer and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap variation between the first signal coupling pads of the first chip and the third signal coupling pads of the second chip is under stringent control of the second distance and the fourth distance. Therefore, the mass-production yield of the semiconductor package is increased.
摘要翻译：半导体封装及其制造方法技术领域本发明涉及半导体封装及其制造方法。半导体封装包括第一芯片和第二芯片。第一芯片包括第一有源表面，至少一个第一非顶部金属层和多个第一信号耦合焊盘。第一非顶部金属层设置成与第一有源表面相邻并间隔开第二距离。第一信号耦合焊盘设置在第一非顶部金属层上。第二芯片电连接到第一芯片。第二芯片包括第二有源表面，至少一个第二非顶部金属层和多个第三信号耦合焊盘。第二活性表面面向第一芯片的第一有效表面。第二非顶部金属层被布置成与第二有源表面相邻并且与第二有源表面间隔开第四距离。第三信号耦合焊盘设置在第二非顶部金属层上，并电容耦合到第一芯片的第一信号耦合焊盘，从而提供第一芯片与第二芯片之间的接近通信。由此，第一芯片的第一信号耦合焊盘与第二芯片的第三信号耦合焊盘之间的间隙变化受到第二距离和第四距离的严格控制。因此，半导体封装的批量生产量增加。

6. 发明申请

US20110233764A1 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件封装及其制造方法
公开(公告)号：US20110233764A1
公开(公告)日：2011-09-29
申请号：US12749191
申请日：2010-03-29
申请人： Hsiao-Chuan CHANG , Tsung-Yueh Tsai , Yi-Shao Lai , Ming-Hsiang Cheng
发明人： Hsiao-Chuan CHANG , Tsung-Yueh Tsai , Yi-Shao Lai , Ming-Hsiang Cheng
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L21/563 , H01L23/48 , H01L23/5389 , H01L23/562 , H01L24/73 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/131 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/30155 , H01L2224/30181 , H01L2224/73103 , H01L2224/73153 , H01L2224/73203 , H01L2224/73204 , H01L2224/92143 , H01L2224/92242 , H01L2224/97 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07811 , H01L2924/00014 , H01L2924/01014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are mechanically disposed on and electrically connected to the first surface and around the cavity, wherein the active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure, wherein the bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.
摘要翻译：公开了一种半导体器件封装及其制造方法。半导体器件封装包括衬底，缓冲结构，两个有源芯片和桥接芯片。衬底具有空腔，第一表面和与第一表面相对的第二表面。空腔从第一表面延伸到第二表面，并且缓冲结构设置在空腔中。有源芯片被机械地设置在第一表面上并且电连接到第一表面并且围绕空腔，其中有源芯片都具有第一有源表面。桥芯片设置在空腔中并且在缓冲结构上方，其中桥芯片具有第二有源表面，第二有源表面面向第一有源表面并与第一有源表面部分重叠，桥芯片用于提供活动芯片之间的邻近通信。

7. 发明申请

US20110156739A1 TEST KIT FOR TESTING A CHIP SUBASSEMBLY AND A TESTING METHOD BY USING THE SAME 审中-公开
标题翻译：用于测试芯片组合的测试工具和使用它的测试方法
公开(公告)号：US20110156739A1
公开(公告)日：2011-06-30
申请号：US12651067
申请日：2009-12-31
申请人： Hsiao-Chuan CHANG , Ming-Hsiang CHENG , Tsung-Yueh TSAI , Yi-Shao LAI , Ming-Kun CHEN
发明人： Hsiao-Chuan CHANG , Ming-Hsiang CHENG , Tsung-Yueh TSAI , Yi-Shao LAI , Ming-Kun CHEN
IPC分类号： G01R31/02 , G01R1/06 , G01R31/26
CPC分类号： G01R1/0433
摘要： A test kit for testing a chip subassembly and a testing method by using the same is provided. The chip subassembly includes at least two stacked chips each having a number of electric contacts is provided. The test kit includes a test socket and a test plate. The test socket is configured to electrically engage the electric contacts on a first side of the chip subassembly. The test plate has at least a number of first probes configured for electrically engaging the electric contacts on a second side of the chip subassembly. At least one of the test socket and the test plate has a number of second probes for electrically connecting the test socket and the test plate.
摘要翻译：提供了用于测试芯片组件的测试工具和使用它的测试方法。芯片组件包括至少两个堆叠的芯片，每个具有多个电触点。测试套件包括测试插座和测试板。测试插座被配置为电连接芯片子组件的第一侧上的电触头。测试板具有至少多个第一探针，其被配置用于电连接芯片子组件的第二侧上的电触头。测试插座和测试板中的至少一个具有用于电连接测试插座和测试板的多个第二探头。

8. 发明申请

US20100157281A1 LASER DISTANCE MEASURING APPARATUS AND CONTROL METHOD THEREOF 有权
标题翻译：激光测距仪及其控制方法
公开(公告)号：US20100157281A1
公开(公告)日：2010-06-24
申请号：US12575569
申请日：2009-10-08
申请人： Yin-Long Luo , Tsung-Yueh Tsai
发明人： Yin-Long Luo , Tsung-Yueh Tsai
IPC分类号： G01C3/08
CPC分类号： G01C3/08 , G01S7/481 , G01S7/497 , G01S17/36
摘要： A laser distance measuring apparatus and control method thereof includes an emitter, a first and second liquid crystal display module, a receiver, a condensing lens, and a control unit. The emitter emits measuring light. The control unit sets the first liquid crystal display module to a second state and the second liquid crystal display module to a first state to receive the reflected light. When the reflected light is larger than a predetermined value, the control unit adjusts a transmittance of the first liquid crystal display module until the reflected light is lower than the predetermined value, and calculates a distance value based on phase difference between the reference light and the reflected light.
摘要翻译：激光测距装置及其控制方法包括发射器，第一和第二液晶显示模块，接收器，聚光透镜和控制单元。发射器发射测量光。控制单元将第一液晶显示模块设置为第二状态，将第二液晶显示模块设置为接收反射光的第一状态。当反射光大于预定值时，控制单元调节第一液晶显示模块的透射率，直到反射光低于预定值，并且基于参考光和第一液晶显示模块之间的相位差来计算距离值反射光。

9. 发明申请

US20090096077A1 Tenon-and-mortise packaging structure 有权
标题翻译：榫眼包装结构
公开(公告)号：US20090096077A1
公开(公告)日：2009-04-16
申请号：US12216637
申请日：2008-07-09
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang , Tsan-Hsien Chen
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang , Tsan-Hsien Chen
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L23/3107 , H01L25/03 , H01L25/16 , H01L2225/0652 , H01L2225/06555 , H01L2225/06586 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.
摘要翻译：提供包括载体和芯片的榫眼包装结构。载体具有与顶表面相对的顶表面和下表面。顶表面形成至少一个榫头突起，并且下表面形成对应于形状，尺寸和位置的榫头突起的榫槽，使得两个载体可以通过将榫头投影连接到彼此并且彼此连接相应的榫槽。榫头和榫槽分别具有导电部分。当榫头突起和榫槽彼此接合时，导电部分彼此电连接。至少一个芯片嵌入在载体中。芯片分别具有有源表面和背面，并与载体的顶表面和下表面电连接。

10. 发明申请

US20070222047A1 Semiconductor package structure 审中-公开
标题翻译：半导体封装结构
公开(公告)号：US20070222047A1
公开(公告)日：2007-09-27
申请号：US11602383
申请日：2006-11-21
申请人： Tsung-Yueh Tsai , Chang-Lin Yeh
发明人： Tsung-Yueh Tsai , Chang-Lin Yeh
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L24/16 , H01L24/31 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/16 , H01L2224/32014 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/73265 , H01L2225/0651 , H01L2225/06555 , H01L2924/01033 , H01L2924/01079 , H01L2924/15153 , H01L2924/15311 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package structure includes a substrate, a first chip, a second chip, a wire, and an encapsulant. The substrate with a cavity has a first surface and a second surface. The cavity penetrates the first surface and the second surface. The first surface and the second surface have a first solder pad and a second solder pad respectively. The first chip having a first active surface and a first non-active surface is disposed inside the cavity. The first active surface has a first contact pad. The second chip having a second active surface and a second non-active surface is disposed on the second surface. The second non-active surface is adhered to the first non-active surface. The second active surface has a second contact pad. The wire is used for electrically connecting the second contact pad and the second solder pad. The encapsulant disposed on the substrate fills the cavity.
摘要翻译：半导体封装结构包括衬底，第一芯片，第二芯片，导线和密封剂。具有空腔的基板具有第一表面和第二表面。空腔穿透第一表面和第二表面。第一表面和第二表面分别具有第一焊盘和第二焊盘。具有第一活性表面和第一非活性表面的第一芯片设置在腔内。第一活性表面具有第一接触垫。具有第二活性表面和第二非活性表面的第二芯片设置在第二表面上。第二非活性表面粘附到第一非活性表面。第二活动表面具有第二接触垫。电线用于电连接第二接触焊盘和第二焊盘。设置在基板上的密封剂填充空腔。

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