专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09070793B2 Semiconductor device packages having electromagnetic interference shielding and related methods 有权
标题翻译：具有电磁干扰屏蔽和相关方法的半导体器件封装
公开(公告)号：US09070793B2
公开(公告)日：2015-06-30
申请号：US13114915
申请日：2011-05-24
申请人： Kuo-Hsien Liao , Chi-Hong Chan , Jian-Cheng Chen , Chian-Her Ueng , Yu-Hsiang Sun
发明人： Kuo-Hsien Liao , Chi-Hong Chan , Jian-Cheng Chen , Chian-Her Ueng , Yu-Hsiang Sun
IPC分类号： H01L23/552 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065
CPC分类号： H01L24/97 , H01L23/3121 , H01L23/49805 , H01L23/552 , H01L24/16 , H01L24/48 , H01L25/0655 , H01L2224/16225 , H01L2224/48227 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/1461 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The semiconductor device package includes a conformal shield layer applied to the exterior surface of the encapsulant, and an internal fence or separation structure embedded in the encapsulant. The fence separates the package into various compartments, with each compartment containing at least one die. The fence thus suppresses EMI between adjacent packages. The package further includes a ground path connected to the internal fence and conformal shield.
摘要翻译：半导体器件封装包括施加到密封剂的外表面的保形屏蔽层和嵌入密封剂中的内部栅栏或分离结构。围栏将包装分成各个隔间，每个隔间至少包含一个模具。因此，围栏可以抑制相邻包装之间的EMI。该封装还包括连接到内部栅栏和保形屏蔽的接地路径。

2. 发明授权

US08436969B2 Photo alignment process and liquid crystal display using the same 有权
标题翻译：照相校准过程和液晶显示使用相同
公开(公告)号：US08436969B2
公开(公告)日：2013-05-07
申请号：US13031230
申请日：2011-02-20
申请人： Yao-Jen Ou , Hang-Lian Lee , Jian-Cheng Chen , Bo-Chin Tsuei
发明人： Yao-Jen Ou , Hang-Lian Lee , Jian-Cheng Chen , Bo-Chin Tsuei
IPC分类号： G02F1/1337
CPC分类号： G02F1/133788
摘要： A photo alignment process and a liquid crystal display using the same are provided. The photo alignment process includes the following steps. A photo alignment material layer is formed on a substrate. The photo alignment material layer is irradiated by a linearly polarized light. A surface of the photo alignment material layer is a first plane. A wave vector of the linearly polarized light is a K vector. A second plane is constructed from a normal vector of the first plane and the K vector. A polarization direction of the linearly polarized light is neither perpendicular nor parallel to the second plane.
摘要翻译：提供光取向处理和使用其的液晶显示器。照片对准过程包括以下步骤。在基板上形成光取向材料层。光线取向材料层被线偏振光照射。光取向材料层的表面是第一平面。线偏振光的波矢是K矢量。第二平面由第一平面和K向量的法向量构成。线偏振光的偏振方向既不垂直也不平行于第二平面。

3. 发明授权

US08212339B2 Semiconductor device packages with electromagnetic interference shielding 有权
标题翻译：具有电磁干扰屏蔽的半导体器件封装
公开(公告)号：US08212339B2
公开(公告)日：2012-07-03
申请号：US12770645
申请日：2010-04-29
申请人： Kuo-Hsien Liao , Jian-Cheng Chen , Chen-Chuan Fan , Chi-Tsung Chiu , Chih-Pin Hung
发明人： Kuo-Hsien Liao , Jian-Cheng Chen , Chen-Chuan Fan , Chi-Tsung Chiu , Chih-Pin Hung
IPC分类号： H01L23/552 , H01L21/78
CPC分类号： H01L23/552 , H01L21/6835 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2221/68331 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.
摘要翻译：这里描述的是具有EMI屏蔽和相关方法的半导体器件封装。在一个实施例中，半导体器件封装包括邻近衬底单元的周边设置并至少部分地在衬底单元的上表面和下表面之间延伸的接地元件。接地元件包括与衬底单元的侧表面相邻设置的凹入部分。半导体器件封装还包括EMI屏蔽，其电连接到接地元件并且与接地元件的凹入部分相邻地向内凹陷。

4. 发明申请

US20100007010A1 SEMICONDUCTOR PACKAGE, METHOD FOR ENHANCING THE BOND OF A BONDING WIRE, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE 有权
标题翻译：半导体封装，用于增强接合线的焊接的方法以及制造半导体封装的方法
公开(公告)号：US20100007010A1
公开(公告)日：2010-01-14
申请号：US12501309
申请日：2009-07-10
申请人： Hsiao Chuan CHANG , Tsung Yueh TSAI , Yi Shao LAI , Ho Ming TONG , Jian Cheng CHEN , Wei Chi YIH , Chang Ying HUNG
发明人： Hsiao Chuan CHANG , Tsung Yueh TSAI , Yi Shao LAI , Ho Ming TONG , Jian Cheng CHEN , Wei Chi YIH , Chang Ying HUNG
IPC分类号： H01L23/49 , H01L21/60 , H01L21/56
CPC分类号： H01L24/85 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48624 , H01L2224/48824 , H01L2224/73265 , H01L2224/78301 , H01L2224/85201 , H01L2224/85375 , H01L2224/8592 , H01L2224/92247 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01079 , H01L2924/07802 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.
摘要翻译：半导体封装的引线接合结构包括接合线，焊盘和非导电粘合材料。接合线包括线部分和块部分，其中块部分物理连接到线部分，并且块部分的截面积大于线部分的截面面积。焊盘粘合到块部分。非导电粘合剂材料覆盖焊盘并密封焊丝的整个块部分。

5. 发明授权

US07256066B2 Flip chip packaging process 有权
标题翻译：倒装芯片封装过程
公开(公告)号：US07256066B2
公开(公告)日：2007-08-14
申请号：US10906890
申请日：2005-03-11
申请人： Jian-Cheng Chen , Yu-Wen Chen , Sheng-Yu Wu
发明人： Jian-Cheng Chen , Yu-Wen Chen , Sheng-Yu Wu
IPC分类号： H01L21/44
CPC分类号： H01L21/563 , H01L21/561 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/351 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： A flip chip packaging process uses an underfill as an encapsultant to reduce the possibility of delamination from occurring due to differential coefficients of thermal expansion, and thus the reliability of a flip chip package structure can be increased. Furthermore, the flooding of the encapsulant over the cutting line need not be taken into consideration for cutting the substrate. Therefore, the usage area of the substrate usage is increased, i.e., more chips can be mounted per unit area of the substrate.
摘要翻译：倒装芯片封装方法使用底部填充剂作为封装剂来减少由于热膨胀系数的差异而发生分层的可能性，因此可以提高倒装芯片封装结构的可靠性。此外，切割基板时，不需要考虑密封剂在切割线上的淹没。因此，增加了基板使用的使用面积，即，可以在基板的每单位面积安装更多的芯片。

6. 发明申请

US20050202593A1 FLIP CHIP PACKAGING PROCESS AND STRUCTURE THEREOF 有权
标题翻译：卷芯片包装工艺及其结构
公开(公告)号：US20050202593A1
公开(公告)日：2005-09-15
申请号：US10906890
申请日：2005-03-11
申请人： Jian-Cheng Chen , Yu-Wen Chen , Sheng-Yu Wu
发明人： Jian-Cheng Chen , Yu-Wen Chen , Sheng-Yu Wu
IPC分类号： H01L21/44 , H01L23/31
CPC分类号： H01L21/563 , H01L21/561 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/351 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： A flip chip packaging process uses an underfill as an encapsultant to reduce the possibility of delamination from occurring due to differential coefficients of thermal expansion, and thus the reliability of a flip chip package structure can be increased. Furthermore, the flooding of the encapsulant over the cutting line need not be taken into consideration for cutting the substrate. Therefore, the usage area of the substrate usage is increased, i.e., more chips can be mounted per unit area of the substrate.
摘要翻译：倒装芯片封装方法使用底部填充剂作为封装剂来减少由于热膨胀系数的差异而发生分层的可能性，因此可以提高倒装芯片封装结构的可靠性。此外，切割基板时，不需要考虑密封剂在切割线上的淹没。因此，增加了基板使用的使用面积，即，可以在基板的每单位面积安装更多的芯片。

7. 发明授权

US08666210B2 Liquid crystal displays and panels 有权
标题翻译：液晶显示器和面板
公开(公告)号：US08666210B2
公开(公告)日：2014-03-04
申请号：US12758989
申请日：2010-04-13
申请人： Chien-Hong Chen , Jian-Cheng Chen , Rung-Nan Lu
发明人： Chien-Hong Chen , Jian-Cheng Chen , Rung-Nan Lu
IPC分类号： G02F1/133 , G02F1/1343 , G02F1/136
CPC分类号： G02F1/133707 , G02F1/133788 , G02F1/134309 , G02F2001/133715 , G02F2001/133742 , G02F2001/133746
摘要： A liquid crystal (LC) display panel including a lower substrate with pixel structures, an upper substrate, and an LC layer is provided. Each of the pixel structures includes a transistor and a pixel electrode. The pixel electrode includes first and second pixel electrodes insulated from each other, respectively including a first pattern and a second pattern that different and complementary to each other. Each of the first pixel electrode and the second pixel electrode has at least a trunk with a width smaller than or equal to 10 microns and a plurality of branches. The LC layer is positioned between the upper and the lower substrates and includes a plurality of LC molecules and a plurality of polymers, which are formed on surfaces of at least one of the upper and the lower substrates to cause the plurality of LC molecules to have a pretilt angle.
摘要翻译：提供了包括具有像素结构的下基板，上基板和LC层的液晶（LC）显示面板。每个像素结构包括晶体管和像素电极。像素电极包括彼此绝缘的第一和第二像素电极，分别包括彼此不同和互补的第一图案和第二图案。第一像素电极和第二像素电极中的每一个至少具有宽度小于或等于10微米的躯干和多个分支。 LC层位于上基板和下基板之间，并且包括多个LC分子和多个聚合物，其形成在上基板和下基板中的至少一个的表面上，以使多个LC分子具有预倾角。

8. 发明授权

US08597860B2 Dummy patterns and method for generating dummy patterns 有权
标题翻译：虚拟模式和生成虚拟模式的方法
公开(公告)号：US08597860B2
公开(公告)日：2013-12-03
申请号：US13111980
申请日：2011-05-20
申请人： Chen-Hua Tsai , Jian-Cheng Chen , Chin-Yueh Tsai , Yao-Jen Fan , Heng-Kun Chen , Hsiang Yang
发明人： Chen-Hua Tsai , Jian-Cheng Chen , Chin-Yueh Tsai , Yao-Jen Fan , Heng-Kun Chen , Hsiang Yang
IPC分类号： G03F1/36 , G03F1/68
CPC分类号： G03F1/70 , G06F17/5072 , G06F2217/12 , H01L21/0334 , H01L23/48 , H01L23/481 , H01L23/528 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.
摘要翻译：一种用于产生虚拟图案的方法包括提供具有第一密度的布局图案的布局区域，在布局图案中插入具有与第一密度对应的第二密度的多个第一伪图案，将布局区域分成多个子图具有第三密度的区域，根据第二密度和第三密度之间的差来调整第一伪图案的尺寸，并将布局图案和第一伪图案输出到光掩模上。

9. 发明授权

US08421986B2 Substrate with multi-domain vertical alignment pixel structure and fabricating method thereof, liquid crystal display panel and liquid crystal display 有权
标题翻译：具有多畴垂直取向像素结构的衬底及其制造方法，液晶显示面板和液晶显示器
公开(公告)号：US08421986B2
公开(公告)日：2013-04-16
申请号：US12980738
申请日：2010-12-29
申请人： Jian-Cheng Chen , Chien-Hong Chen , Chih-Yung Hsieh , Wei Lo , Chun-Hsu Lin , Ching-Che Yang , Jia-Lun Chen
发明人： Jian-Cheng Chen , Chien-Hong Chen , Chih-Yung Hsieh , Wei Lo , Chun-Hsu Lin , Ching-Che Yang , Jia-Lun Chen
IPC分类号： G02F1/1333 , G02F1/1337 , G02F1/1343
CPC分类号： G02F1/134336 , G02F1/133707 , G02F1/133753 , G02F1/1393 , G02F2001/133796
摘要： A substrate with a multi-domain vertical alignment pixel structure is provided. The substrate is opposite to a counter substrate with a common electrode, and a liquid crystal layer is disposed between the substrate and the counter substrate. The substrate includes a scan line and a data line, an active device, first and second patterned pixel electrodes and a voltage drop layer. Wherein, the first patterned pixel electrode provides a first electrical field to the liquid crystal layer, and the second patterned pixel electrode provides a second electrical field to the liquid crystal layer. The voltage drop layer makes the first electrical field smaller than the second electrical field.
摘要翻译：提供具有多域垂直对准像素结构的衬底。基板与具有公共电极的对置基板相对，并且液晶层设置在基板和对置基板之间。衬底包括扫描线和数据线，有源器件，第一和第二图案化像素电极和电压降层。其中，第一图案化像素电极向液晶层提供第一电场，第二图案化像素电极为液晶层提供第二电场。电压降层使得第一电场小于第二电场。

10. 发明授权

US08247889B2 Package having an inner shield and method for making the same 有权
标题翻译：具有内屏蔽的封装及其制造方法
公开(公告)号：US08247889B2
公开(公告)日：2012-08-21
申请号：US12856389
申请日：2010-08-13
申请人： Kuo-Hsien Liao , Jian-Cheng Chen
发明人： Kuo-Hsien Liao , Jian-Cheng Chen
IPC分类号： H01L23/552 , H01L23/58
CPC分类号： H05K9/0022 , H01L23/552 , H01L25/0655 , H01L2224/16225 , H01L2224/97 , H01L2924/3025 , H05K1/0218 , H05K3/284 , H05K2201/09972 , H05K2203/1316 , Y10T29/49146 , H01L2224/81
摘要： The present invention relates to a package having an inner shield and a method for making the same. The package includes a substrate, a plurality of electrical elements, a molding compound, an inner shield and a conformal shield. The electrical elements are disposed on the substrate. The molding compound is disposed on a surface of the substrate, encapsulates the electrical elements, and includes at least one groove. The groove penetrates a top surface and a bottom surface of the molding compound and is disposed between the electrical elements, and there is a gap between a short side of the groove and a side surface of the molding compound. The inner shield is disposed in the groove and electrically connected to the substrate. The conformal shield covers the molding compound and a side surface of the substrate, and electrically connects the substrate and the inner shield. Therefore, the inner shield enables the electrical elements to have low electromagnetic interference and high electromagnetic compatibility.
摘要翻译：本发明涉及具有内屏蔽的封装及其制造方法。封装包括基板，多个电气元件，模塑料，内护罩和保形罩。电气元件设置在基板上。模塑料被设置在基板的表面上，封装电气元件，并且包括至少一个凹槽。凹槽穿过模制化合物的顶表面和底表面并且设置在电气元件之间，并且在凹槽的短边和模塑料的侧表面之间存在间隙。内屏蔽件设置在凹槽中并电连接到基板。共形屏蔽覆盖模塑料和基板的侧表面，并且电连接基板和内屏蔽。因此，内部屏蔽使得电气元件具有低电磁干扰和高电磁兼容性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式