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1. 发明授权

US06717231B2 Trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
标题翻译：沟槽隔离区域在其中具有防止过蚀刻的凹陷抑制层
公开(公告)号：US06717231B2
公开(公告)日：2004-04-06
申请号：US10224017
申请日：2002-08-20
申请人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
发明人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
摘要翻译：形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。掩模层可以包括氮化硅。然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。接下来，在凹陷抑制层上形成应力消除层。该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。然后用沟槽隔离层填充沟槽。然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

2. 发明授权

US06461937B1 Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
标题翻译：形成其中具有防止过蚀刻的凹陷抑制层的沟槽隔离区的方法
公开(公告)号：US06461937B1
公开(公告)日：2002-10-08
申请号：US09479442
申请日：2000-01-07
申请人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
发明人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
摘要翻译：形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。掩模层可以包括氮化硅。然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。接下来，在凹陷抑制层上形成应力消除层。该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。然后用沟槽隔离层填充沟槽。然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

3. 发明授权

US6093622A Isolation method of semiconductor device using second pad oxide layer formed through chemical vapor deposition (CVD) 失效
标题翻译：使用通过化学气相沉积（CVD）形成的第二衬垫氧化物层的半导体器件的隔离方法
公开(公告)号：US6093622A
公开(公告)日：2000-07-25
申请号：US148060
申请日：1998-09-04
申请人： Dong-ho Ahn , Sung-eui Kim , Yu-gyun Shin
发明人： Dong-ho Ahn , Sung-eui Kim , Yu-gyun Shin
IPC分类号： H01L21/285 , H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76202
摘要： An isolation method in the fabrication process of a semiconductor device is provided. The method forms an oxide layer as a buffer layer for reducing stress through chemical vapor deposition (CVD). By the method, a first pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate, and then an silicon nitride layer pattern is formed by patterning, and undercuts are formed in the first pad oxide layer pattern. Subsequently, a second pad oxide layer is formed on the entire surface of the semiconductor substrate through CVD, and then spacers are formed on the sidewalls of both the patterned first pad oxide layer and silicon nitride layer and a field oxide layer is formed through thermal oxidation. Alternatively, a silicon layer is deposited without the spacers to form the field oxide layer. The second pad oxide layer is a buffer layer for buffering stress during formation of the field oxide layer.
摘要翻译：提供了半导体器件的制造工艺中的隔离方法。该方法形成通过化学气相沉积（CVD）来减少应力的缓冲层的氧化物层。通过该方法，在半导体衬底上形成第一衬垫氧化物层和氮化硅层，然后通过图案形成氮化硅层图案，并且在第一衬垫氧化物层图案中形成底切。随后，通过CVD在半导体衬底的整个表面上形成第二焊盘氧化物层，然后在图案化的第一焊盘氧化物层和氮化硅层的侧壁上形成间隔物，并且通过热氧化形成场氧化物层。或者，沉积硅层而没有间隔物以形成场氧化物层。第二衬垫氧化物层是用于在形成场氧化物层期间缓冲应力的缓冲层。

4. 发明申请

US20080017908A1 Semiconductor memory device and method of fabricating the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20080017908A1
公开(公告)日：2008-01-24
申请号：US11826590
申请日：2007-07-17
申请人： Min-hee Cho , Sung-eui Kim , Won-tae Hwang , Jin-hye Bae
发明人： Min-hee Cho , Sung-eui Kim , Won-tae Hwang , Jin-hye Bae
IPC分类号： H01L29/94 , H01L21/8242
CPC分类号： H01L28/90 , H01L27/10817 , H01L27/10855
摘要： Exemplary embodiments relate to a semiconductor memory device and method of fabricating the same. The semiconductor member device may include a semiconductor substrate, a plurality of storage node contact plugs formed above the semiconductor substrate, and a plurality of storage node electrodes, each of the plurality of storage node electrodes may be located respectively above each of the plurality of storage node contact plugs. Each of the storage node electrodes may include a cylindrical body and a generally Y-shaped connection portion extending from the cylindrical body and interfacing the storage node contact plugs.
摘要翻译：示例性实施例涉及一种半导体存储器件及其制造方法。半导体构件装置可以包括半导体衬底，形成在半导体衬底上的多个存储节点接触插塞和多个存储节点电极，多个存储节点电极中的每一个可以分别位于多个存储器中的每一个上节点接触插头。每个存储节点电极可以包括圆柱形主体和从圆柱形主体延伸并且与存储节点接触插塞接口的大致Y形的连接部分。

5. 发明授权

US5824594A Integrated circuit device isolating methods including silicon spacers and oxidation barrier films 失效
标题翻译：集成电路器件隔离方法，包括硅隔离层和氧化阻挡膜
公开(公告)号：US5824594A
公开(公告)日：1998-10-20
申请号：US837208
申请日：1997-04-14
申请人： Sung-eui Kim , Young-dae Kim
发明人： Sung-eui Kim , Young-dae Kim
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76205
摘要： An integrated circuit device is isolated by forming a pad oxide layer on an integrated circuit substrate. A mask pattern is formed on the pad layer. The mask pattern includes sidewalls which selectively expose the pad oxide layer between the sidewalls. A silicon spacer is formed on the sidewalls. An oxidation barrier film is formed on the silicon spacer and on the exposed pad oxide layer. The integrated circuit substrate is then oxidized through the oxidation barrier film to form a device isolating layer. The oxidation barrier film on the exposed pad oxide layer is thinner than the oxidation barrier film on the sidewalls. Thus, oxidation of the silicon spacer is delayed relative to the substrate.
摘要翻译：通过在集成电路基板上形成衬垫氧化物层来隔离集成电路器件。在衬垫层上形成掩模图案。掩模图案包括侧壁，其选择性地暴露在侧壁之间的焊盘氧化物层。在侧壁上形成硅衬垫。在硅间隔物和暴露的焊盘氧化物层上形成氧化阻挡膜。然后将集成电路基板氧化通过氧化阻挡膜以形成器件隔离层。暴露的焊盘氧化物层上的氧化阻挡膜比侧壁上的氧化阻挡膜薄。因此，硅衬垫的氧化相对于衬底延迟。

6. 发明授权

US06723662B2 Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with reduced chloride 有权
标题翻译：在使用减少氯化物的湿法或干法氧化法的集成电路器件中形成栅极氧化膜的方法
公开(公告)号：US06723662B2
公开(公告)日：2004-04-20
申请号：US10630101
申请日：2003-07-30
申请人： Kong-soo Lee , Jae-jong Han , Sung-eui Kim
发明人： Kong-soo Lee , Jae-jong Han , Sung-eui Kim
IPC分类号： H01L218242
CPC分类号： H01L21/28185 , H01L21/02164 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02274 , H01L21/02304 , H01L21/02337 , H01L21/28211 , H01L21/31662 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/10894 , H01L27/11
摘要： Methods of forming gate oxide films in integrated circuit devices using wet or dry oxidization processes with a reduced amount of chloride are disclosed. A gate oxide film is formed on a substrate on an active region adjacent to a trench isolation region in a first gas atmosphere with a first amount of chloride. The gate oxide film is annealed in a second gas atmosphere including a second amount of chloride that is greater than the first amount.
摘要翻译：公开了使用具有减少量的氯化物的湿式或干式氧化方法在集成电路器件中形成栅极氧化膜的方法。在具有第一量氯化物的第一气体气氛中的与沟槽隔离区相邻的有源区上的衬底上形成栅极氧化膜。栅极氧化膜在包括大于第一量的第二量氯化物的第二气体气氛中退火。

7. 发明授权

US5677232A Methods of fabricating combined field oxide/trench isolation regions 失效
标题翻译：组合场氧化物/沟槽隔离区域的方法
公开(公告)号：US5677232A
公开(公告)日：1997-10-14
申请号：US754889
申请日：1996-11-22
申请人： Sung-eui Kim , Soo-jin Hong
发明人： Sung-eui Kim , Soo-jin Hong
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76202 , H01L21/76229 , H01L21/76235
摘要： An isolation region is formed on a substrate by forming spaced apart mesas on the substrate. A first insulation region is then formed on the substrate and second insulation regions are formed on the mesas, the first insulation region being disposed between and spaced apart from a respective one of the mesas, a respective one of the second insulation regions capping a respective one of the mesas. Preferably, the first and second insulation regions are formed by forming sidewall spacers adjacent sidewall portions of the mesas and oxidizing portions of the mesas opposite the substrate and a portion of the substrate disposed between the sidewall spacers. Spaced apart trenches are formed in the substrate on opposite sides of the first insulation region, a respective one of the trenches being disposed between the first insulation region and a respective one of the mesas, preferably by removing the sidewall spacers and underlying portions of the substrate. An insulating layer is formed on the substrate, filling the trenches and covering the first insulation region, and the substrate is planarized to remove portions of the insulating layer and the second insulation regions and thereby expose underlying portions of the mesas and leave a third insulation region spanning the trenches.
摘要翻译：通过在衬底上形成间隔开的台面，在衬底上形成隔离区。然后在基板上形成第一绝缘区域，并且在台面上形成第二绝缘区域，第一绝缘区域设置在相应的一个台面之间并与相应的一个台面间隔开，第一绝缘区域中的相应一个覆盖相应的一个的台面。优选地，第一和第二绝缘区域通过形成邻近台面的侧壁部分的侧壁间隔和与衬底相对的台面的氧化部分和设置在侧壁间隔件之间的衬底的一部分而形成。隔开的沟槽在第一绝缘区域的相对侧上的衬底中形成，相应的沟槽设置在第一绝缘区域和相应的台面之间，优选地通过去除侧壁间隔件和衬底的下面部分。在衬底上形成绝缘层，填充沟槽并覆盖第一绝缘区域，并且将衬底平坦化以去除绝缘层和第二绝缘区域的部分，从而暴露台面的下面部分并留下第三绝缘区域跨越壕沟

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