专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08627036B2 Memory management techniques 有权
公开(公告)号：US08627036B2
公开(公告)日：2014-01-07
申请号：US13230109
申请日：2011-09-12
申请人： Steve Pronovost , Maxwell Abernethy , Rudolph Balaz , Ameet Chitre
发明人： Steve Pronovost , Maxwell Abernethy , Rudolph Balaz , Ameet Chitre
IPC分类号： G06F12/00
CPC分类号： G06F12/023 , G06F9/5016 , G06F9/5022 , G06F12/02 , G06F12/0638 , G06F12/0891 , G06F2212/1044 , G06F2212/657 , G06T1/60 , G09G5/001
摘要： Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.

2. 发明申请

US20090290709A1 HARDWARE-BASED OUTPUT PROTECTION OF MULTIPLE VIDEO STREAMS 有权
标题翻译：基于硬件的多路视频输出保护
公开(公告)号：US20090290709A1
公开(公告)日：2009-11-26
申请号：US12124899
申请日：2008-05-21
申请人： DONALD SCOTT MACDONALD , STEVE PRONOVOST , PATRIK SCHNELL
发明人： DONALD SCOTT MACDONALD , STEVE PRONOVOST , PATRIK SCHNELL
IPC分类号： H04N7/167
CPC分类号： H04N21/835 , G11B20/00086 , G11B20/0021 , G11B20/00507 , G11B20/10527 , G11B2020/1062 , G11B2220/61 , H04N21/4325 , H04N21/4405
摘要： Computer-readable media, computerized methods, and computer systems for managing dynamic allocation of one or more protected memory segments for storing content of secure data are provided. Initially, the secure data is recognized as being carried by a media stream being communicated from a media-reading device. One or more protected target segments and protected target segments are instantiated, where these protected memory segments are protected from illicit access by hardware-based rules. Regions of hardware memory are dynamically allocated to hold these protected memory segments and the secure data is iteratively written thereto. The protected source segments are associating with the media stream based on a license attached thereto, while the protected target segments are associating with presentation devices based on a standard of output protection supported thereby. Accordingly, the protected source segments are mapped to the protected target segments according to whether the license encompasses the standard of the output protection.
摘要翻译：提供了用于管理用于存储安全数据的内容的一个或多个受保护的存储器段的动态分配的计算机可读介质，计算机化方法和计算机系统。最初，安全数据被识别为由从媒体读取设备传送的媒体流携带。一个或多个受保护的目标段和受保护的目标段被实例化，其中这些受保护的存储器段被基于硬件的规则保护而不被非法访问。动态地分配硬件存储器的区域以保存这些受保护的存储器段，并且将安全数据迭代地写入其中。受保护的源段基于附加到其上的许可证与媒体流相关联，而受保护的目标段基于由其支持的输出保护的标准与呈现设备相关联。因此，根据许可证是否包含输出保护的标准，受保护的源段被映射到受保护的目标段。

3. 发明申请

US20080301687A1 SYSTEMS AND METHODS FOR ENHANCING PERFORMANCE OF A COPROCESSOR 有权
标题翻译：用于提高共处理器性能的系统和方法
公开(公告)号：US20080301687A1
公开(公告)日：2008-12-04
申请号：US12172910
申请日：2008-07-14
申请人： Anuj B. Gosalia , Steve Pronovost
发明人： Anuj B. Gosalia , Steve Pronovost
IPC分类号： G06F9/46
CPC分类号： G06F9/5038 , G06F9/30087 , G06F9/461 , G06F9/4843 , G06F9/5016 , G06F9/544 , G06F9/546 , Y02D10/22 , Y02D10/24
摘要： Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.
摘要翻译：用于最小化协处理器“饥饿”的技术，并且用于在协处理器中有效地调度处理以获得更高的效率和功率。提供运行列表，允许协处理器从一个任务切换到下一个任务，而不必等待CPU干预。称为“表面故障”的方法允许协处理器在大任务开始时发生故障，而不是在任务中间的任何地方。可以将DMA控制指令，即“围栏”，“陷阱”和“启用/禁用上下文切换”插入到处理流中，以使协处理器执行增强协处理器效率和功率的任务。这些指令也可用于构建高级同步对象。最后，描述了一种“翻转”技术，其可以将显示器的基准基准从一个位置切换到另一个位置，从而改变整个显示表面。

4. 发明授权

US07421694B2 Systems and methods for enhancing performance of a coprocessor 有权
标题翻译：用于增强协处理器性能的系统和方法
公开(公告)号：US07421694B2
公开(公告)日：2008-09-02
申请号：US10763778
申请日：2004-01-22
申请人： Anuj B. Gosalia , Steve Pronovost
发明人： Anuj B. Gosalia , Steve Pronovost
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/4843 , G06F9/4881 , G06F9/5016 , Y02D10/22 , Y02D10/24
摘要： Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.
摘要翻译：用于最小化协处理器“饥饿”的技术，并且用于在协处理器中有效地调度处理以获得更高的效率和功率。提供运行列表，允许协处理器从一个任务切换到下一个任务，而不必等待CPU干预。称为“表面故障”的方法允许协处理器在大任务开始时发生故障，而不是在任务中间的任何地方。可以将DMA控制指令，即“围栏”，“陷阱”和“启用/禁用上下文切换”插入到处理流中，以使协处理器执行增强协处理器效率和功率的任务。这些指令也可用于构建高级同步对象。最后，描述了一种“翻转”技术，其可以将显示器的基准基准从一个位置切换到另一个位置，从而改变整个显示表面。

5. 发明授权

US09342322B2 System and method for layering using tile-based renderers 有权
标题翻译：使用基于瓦片的渲染器进行分层的系统和方法
公开(公告)号：US09342322B2
公开(公告)日：2016-05-17
申请号：US13230436
申请日：2011-09-12
申请人： Blake D. Pelton , Amar Patel , Steve Pronovost
发明人： Blake D. Pelton , Amar Patel , Steve Pronovost
IPC分类号： G06F9/44 , G06T11/40 , G09G5/36 , G06F17/00 , G06T1/00 , G06T15/00
CPC分类号： G06T11/40 , G06F9/44 , G06F9/451 , G06F17/00 , G06T1/00 , G06T1/20 , G06T15/00 , G06T15/005 , G09G5/36 , G09G5/363 , G09G2360/122
摘要： A method for tile-based rendering of content. Content may be rendered in a memory region organized as multiple tiles. In scenarios in which content is generated in layers, for operations that involve compositing image layers, an order in which portions of the image are processed may be selected to reduce the aggregate number of memory accesses times, which in turn may improve the performance of a computer that uses tile-based rendering. An image may be processed such that operations relating to rendering portions of different layers corresponding to the same tile are performed sequentially. Such processing may be used in a computer with a graphics processing unit that supports tile-based rendering, and may be particularly well suited for computers with a slate form factor. An interface to a graphics processing utility within the computer may provide a flag to allow an application to specify whether operations may be reordered.
摘要翻译：一种基于图块的内容呈现方法。内容可以在被组织为多个瓦片的存储器区域中呈现。在层内生成内容的情况下，对于涉及合成图像层的操作，可以选择处理图像的哪些部分的顺序来减少存储器访问次数的总数，这又可以提高图像的性能计算机使用基于瓦片的渲染。可以处理图像，使得与依次对应的不同层的渲染部分相关的操作被顺序地执行。这种处理可以在具有支持基于瓦片的呈现的图形处理单元的计算机中使用，并且可以特别适合于具有平板形状因数的计算机。与计算机内的图形处理实用程序的接口可以提供标志以允许应用程序指定是否可以重新排序操作。

6. 发明授权

US09298498B2 Building a run list for a coprocessor based on rules when the coprocessor switches from one context to another context 有权
标题翻译：当协处理器从一个上下文切换到另一个上下文时，基于规则构建协处理器的运行列表
公开(公告)号：US09298498B2
公开(公告)日：2016-03-29
申请号：US12172910
申请日：2008-07-14
申请人： Anuj B. Gosalia , Steve Pronovost
发明人： Anuj B. Gosalia , Steve Pronovost
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50 , G06F9/30 , G06F9/54
CPC分类号： G06F9/5038 , G06F9/30087 , G06F9/461 , G06F9/4843 , G06F9/5016 , G06F9/544 , G06F9/546 , Y02D10/22 , Y02D10/24
摘要： Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.
摘要翻译：用于最小化协处理器“饥饿”的技术，并且用于在协处理器中有效地调度处理以获得更高的效率和功率。提供运行列表，允许协处理器从一个任务切换到下一个任务，而不必等待CPU干预。称为“表面故障”的方法允许协处理器在大任务开始时发生故障，而不是在任务中间的任何地方。可以将DMA控制指令，即“围栏”，“陷阱”和“启用/禁用上下文切换”插入到处理流中，以使协处理器执行增强协处理器效率和功率的任务。这些指令也可用于构建高级同步对象。最后，描述了一种“翻转”技术，其可以将显示器的基准基准从一个位置切换到另一个位置，从而改变整个显示表面。

7. 发明授权

US08671411B2 Multithreaded kernel for graphics processing unit 有权
标题翻译：用于图形处理单元的多线程内核
公开(公告)号：US08671411B2
公开(公告)日：2014-03-11
申请号：US12657278
申请日：2010-01-15
申请人： Anuj B. Gosalia , Steve Pronovost
发明人： Anuj B. Gosalia , Steve Pronovost
IPC分类号： G06F9/46 , G06F3/00 , G06T1/00
CPC分类号： G06F9/5038 , G06F9/30087 , G06F9/461 , G06F9/4843 , G06F9/5016 , G06F9/544 , G06F9/546 , Y02D10/22 , Y02D10/24
摘要： Systems and methods are provided for scheduling the processing of a coprocessor whereby applications can submit tasks to a scheduler, and the scheduler can determine how much processing each application is entitled to as well as an order for processing. In connection with this process, tasks that require processing can be stored in physical memory or in virtual memory that is managed by a memory manager. The invention also provides various techniques of determining whether a particular task is ready for processing. A “run list” may be employed to ensure that the coprocessor does not waste time between tasks or after an interruption. The invention also provides techniques for ensuring the security of a computer system, by not allowing applications to modify portions of memory that are integral to maintaining the proper functioning of system operations.
摘要翻译：提供了用于调度协处理器的处理的系统和方法，由此应用可以将任务提交给调度器，并且调度器可以确定每个应用程序被处理多少处理以及处理顺序。关于这个过程，需要处理的任务可以被存储在由存储器管理器管理的物理存储器或虚拟存储器中。本发明还提供了确定特定任务是否准备好进行处理的各种技术。可以使用“运行列表”来确保协处理器不会在任务之间或在中断之后浪费时间。本发明还提供了用于确保计算机系统的安全性的技术，不允许应用修改为维持系统操作的正常功能而整体的部分存储器。

8. 发明授权

US07673304B2 Multithreaded kernel for graphics processing unit 有权
公开(公告)号：US07673304B2
公开(公告)日：2010-03-02
申请号：US10763777
申请日：2004-01-22
申请人： Anuj B. Gosalia , Steve Pronovost
发明人： Anuj B. Gosalia , Steve Pronovost
IPC分类号： G06F9/46 , G06F15/167
CPC分类号： G06F9/5038 , G06F9/30087 , G06F9/461 , G06F9/4843 , G06F9/5016 , G06F9/544 , G06F9/546 , Y02D10/22 , Y02D10/24
摘要： Systems and methods are provided for scheduling the processing of a coprocessor whereby applications can submit tasks to a scheduler, and the scheduler can determine how much processing each application is entitled to as well as an order for processing. In connection with this process, tasks that require processing can be stored in physical memory or in virtual memory that is managed by a memory manager. The invention also provides various techniques of determining whether a particular task is ready for processing. A “run list” may be employed to ensure that the coprocessor does not waste time between tasks or after an interruption. The invention also provides techniques for ensuring the security of a computer system, by not allowing applications to modify portions of memory that are integral to maintaining the proper functioning of system operations.

9. 发明申请

US20090132769A1 STATISTICAL COUNTING FOR MEMORY HIERARCHY OPTIMIZATION 审中-公开
标题翻译：用于记忆层次优化的统计计数
公开(公告)号：US20090132769A1
公开(公告)日：2009-05-21
申请号：US11942259
申请日：2007-11-19
申请人： Steve Pronovost , Ketan K. Dalal , Ameet A. Chitre
发明人： Steve Pronovost , Ketan K. Dalal , Ameet A. Chitre
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/122 , G06F12/08
摘要： Systems and methods that optimize memory allocation in hierarchical and/or distributed data storage. A memory management component facilitates a compact manner of identifying approximately how often the memory chunk is being used, to promote efficient operation of the system as a whole. Each memory location can be changed based on the corresponding memory access that is determined through tracking of statistical usage counts of memory locations, and a comparison thereof with a threshold value.
摘要翻译：优化分层和/或分布式数据存储中内存分配的系统和方法。存储器管理组件有助于紧凑地识别存储块被使用的频率，以促进整个系统的有效操作。可以基于通过跟踪存储器位置的统计使用计数确定的相应存储器访问以及与阈值的比较来改变每个存储器位置。

10. 发明申请

US20080109810A1 PARALLEL ENGINE SUPPORT IN DISPLAY DRIVER MODEL 有权
标题翻译：显示驱动器模型中的并行发动机支持
公开(公告)号：US20080109810A1
公开(公告)日：2008-05-08
申请号：US11557301
申请日：2006-11-07
申请人： Steve Pronovost , Anuj B. Gosalia , Ameet Arun Chitre
发明人： Steve Pronovost , Anuj B. Gosalia , Ameet Arun Chitre
IPC分类号： G06F9/50
CPC分类号： G06F9/4843 , G06F3/14 , G06F9/461 , G06F9/5016 , G06F9/5061 , G06F9/544 , G06T7/0004 , G09G5/363
摘要： Systems and methods that independently control divided and/or isolated processing resources of a Graphical Processing Unit (GPU). Synchronization primitives for processing are shared among such resources to process interaction with the engines and their associated different requirements (e.g. different language). Accordingly, independent threads can be created against particular nodes (e.g., a video engine node, 3D engine node), wherein multiple engines can exist under a single node, and independent control can subsequently be exerted upon the plurality of engines associated with the GPU.
摘要翻译：独立控制图形处理单元（GPU）的分割和/或隔离处理资源的系统和方法。用于处理的同步原语在这些资源之间共享以处理与引擎及其相关联的不同要求（例如不同语言）的交互。因此，可以针对特定节点（例如，视频引擎节点，3D引擎节点）创建独立线程，其中多个引擎可以存在于单个节点下，并且随后可以在与GPU相关联的多个引擎上施加独立控制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式