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1. 发明授权

US07869590B2 Method and system for hardware accelerator for implementing f9 integrity algorithm in WCDMA compliant handsets 有权
标题翻译：用于在WCDMA兼容手机中实现f9完整性算法的硬件加速器的方法和系统
公开(公告)号：US07869590B2
公开(公告)日：2011-01-11
申请号：US11103705
申请日：2005-04-12
申请人： Srinivasan Surendran , Ruei-Shiang Suen
发明人： Srinivasan Surendran , Ruei-Shiang Suen
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28
CPC分类号： H04L9/0625 , H04L9/3242 , H04L2209/125 , H04L2209/24 , H04L2209/38 , H04L2209/80
摘要： In a wireless communication system, a method and system for a hardware accelerator for implementing the f9 integrity algorithm in WCDMA compliant handsets are provided. Intermediate variables may be initialized in an integrity function and a first processing block of bits and at least one additional processing block of bits may be generated for the integrity function from a padded string generated from input variables. Values for a first and a second processing variable may be generated for each processing stage based on a corresponding processing block of bits and on immediately generated previous first and second processing values. The first processing value may be generated utilizing a KASUMI operation after an indication that an immediately previous generated first processing value is available. An authentication code may be generated based on a last of the second processing values and a modified integrity key.
摘要翻译：在无线通信系统中，提供了一种用于在WCDMA兼容手机中实现f9完整性算法的硬件加速器的方法和系统。可以在完整性函数中初始化中间变量，并且可以从从输入变量生成的填充字符串为完整性函数生成位的第一处理块和位的至少一个附加处理块。可以基于相应的位的处理块和立即生成的先前的第一和第二处理值，为每个处理级产生第一和第二处理变量的值。可以在紧接着之前生成的第一处理值可用的指示之后利用KASUMI操作来生成第一处理值。可以基于最后的第二处理值和修改的完整性密钥来生成认证码。

2. 发明授权

US07760874B2 Method and system for implementing FI function in KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets 失效
标题翻译：用于在GSM / GPRS / EDGE兼容手机中加速加密的KASUMI算法中实现FI功能的方法和系统
公开(公告)号：US07760874B2
公开(公告)日：2010-07-20
申请号：US10924219
申请日：2004-08-23
申请人： Ruei-Shiang Suen , Srinivasan Surendran
发明人： Ruei-Shiang Suen , Srinivasan Surendran
IPC分类号： H04L9/28 , H04L9/06 , H04K1/00
CPC分类号： H04L9/0625 , H04L2209/125 , H04L2209/24 , H04L2209/80
摘要： In a wireless communication system, a method and system for implementing an FI function in a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. An efficient implementation of the FI function may comprise a first substitution stage and a second substitution stage, where a 9-bit substitution circuit and a 7-bit substitution circuit may be used in each of the stages. A pipe register may be used to transfer and zero-extend an input to the 7-bit substitution circuit for processing with an output of the 9-bit substitution circuit. A first multiplexer and a second multiplexer may be used to select the inputs for the substitution circuits at each one of the substitution stages. A third multiplexer and a fourth multiplexer may be used to select subkeys for encryption during the first substitution stage and zero value signals during the second substitution stage.
摘要翻译：在无线通信系统中，提供了一种用于在KASUMI算法中实现FI功能的方法和系统，用于在GSM / GPRS / EDGE兼容手机中加速加密。 FI功能的有效实现可以包括第一替换阶段和第二替换阶段，其中可以在每个阶段中使用9位替换电路和7位替换电路。可以使用管道寄存器来将输入传递和零扩展到7位替换电路，以便用9位替代电路的输出进行处理。可以使用第一多路复用器和第二多路复用器在每个替代级选择替代电路的输入。可以使用第三多路复用器和第四多路复用器来选择在第一替换阶段期间进行加密的子密钥和在第二替换阶段期间的零值信号。

3. 发明申请

US20060177050A1 Method and system for hardware accelerator for implementing f8 confidentiality algorithm in WCDMA compliant handsets 失效
公开(公告)号：US20060177050A1
公开(公告)日：2006-08-10
申请号：US11053099
申请日：2005-02-08
申请人： Srinivasan Surendran , Ruei-Shiang Suen
发明人： Srinivasan Surendran , Ruei-Shiang Suen
IPC分类号： H04L9/28
CPC分类号： H04L9/0662 , H04L9/0625 , H04L63/0428 , H04L2209/125 , H04L2209/24 , H04L2209/80
摘要： In a wireless communication system, a method and system for hardware accelerator for implementing the f8 confidentiality algorithm in WCDMA compliant handsets are provided. Input variables may be initialized in a keystream generator and an intermediate value may be generated with a confidentiality key parameter and a key modifier. The number of processing blocks of output bits may be based on the length of the input bitstream. The processing blocks of output bits may be generated utilizing a KASUMI operation and may be based on an immediately previous processing block of output bits, the intermediate value, and an indication of the current processing block of output bits. The processing blocks of output bits may be generated after an indication that an immediately previous processing block of output bits is available. The keystream generator may indicate when a first and any additional processing blocks of output bits have been determined.

4. 发明申请

US20060013388A1 Method and system for implementing FI function in KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets 失效
标题翻译：用于在GSM / GPRS / EDGE兼容手机中加速加密的KASUMI算法中实现FI功能的方法和系统
公开(公告)号：US20060013388A1
公开(公告)日：2006-01-19
申请号：US10924219
申请日：2004-08-23
申请人： Ruei-Shiang Suen , Srinivasan Surendran
发明人： Ruei-Shiang Suen , Srinivasan Surendran
IPC分类号： H04L9/28
CPC分类号： H04L9/0625 , H04L2209/125 , H04L2209/24 , H04L2209/80
摘要： In a wireless communication system, a method and system for implementing an FI function in a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. An efficient implementation of the FI function may comprise a first substitution stage and a second substitution stage, where a 9-bit substitution circuit and a 7-bit substitution circuit may be used in each of the stages. A pipe register may be used to transfer and zero-extend an input to the 7-bit substitution circuit for processing with an output of the 9-bit substitution circuit. A first multiplexer and a second multiplexer may be used to select the inputs for the substitution circuits at each one of the substitution stages. A third multiplexer and a fourth multiplexer may be used to select subkeys for encryption during the first substitution stage and zero value signals during the second substitution stage.
摘要翻译：在无线通信系统中，提供了一种用于在KASUMI算法中实现FI功能的方法和系统，用于在GSM / GPRS / EDGE兼容手机中加速加密。 FI功能的有效实现可以包括第一替换阶段和第二替换阶段，其中可以在每个阶段中使用9位替换电路和7位替换电路。可以使用管道寄存器来将输入传递和零扩展到7位替换电路，以便用9位替代电路的输出进行处理。可以使用第一多路复用器和第二多路复用器在每个替代级选择替代电路的输入。可以使用第三多路复用器和第四多路复用器来选择在第一替换阶段期间进行加密的子密钥和在第二替换阶段期间的零值信号。

5. 发明申请

US20060039553A1 Method and system for implementing the A5/3 encryption algorithm for GSM and EDGE compliant handsets 失效
公开(公告)号：US20060039553A1
公开(公告)日：2006-02-23
申请号：US10924214
申请日：2004-08-23
申请人： Ruei-Shiang Suen , Srinivasan Surendran
发明人： Ruei-Shiang Suen , Srinivasan Surendran
IPC分类号： H04L9/28
CPC分类号： H04L9/065 , H04L2209/125 , H04L2209/24 , H04L2209/80
摘要： In a wireless communication system, a method and system for implementing the A5/3 encryption algorithm for GSM and EDGE compliant handsets are provided. Input variables may be initialized in a keystream generator and an intermediate value may be generated with a cipher key parameter and a key modifier. A number of processing blocks of output bits may be determined based on a number of bits in an output keystream. The processing blocks of output bits may be generated utilizing a KASUMI operation and may be based on an immediately previous processing block of output bits, the intermediate value, and an indication of the processing block of output bits being processed. The processing blocks of output bits may be generated after an indication that an immediately previous processing block of output bits is available and may be grouped into two final blocks of output bits in the output keystream.

6. 发明授权

US06204781B1 General rate N/(N+1) (0, G) code construction for data coding 有权
标题翻译：通用速率N /（N + 1）（0，G）代码构建用于数据编码
公开(公告)号：US06204781B1
公开(公告)日：2001-03-20
申请号：US09272089
申请日：1999-03-18
申请人： Pervez M. Aziz , Ian M. Hughes , Patrick W. Kempsey , Srinivasan Surendran
发明人： Pervez M. Aziz , Ian M. Hughes , Patrick W. Kempsey , Srinivasan Surendran
IPC分类号： H03M700
CPC分类号： H03M7/46 , G06T9/005
摘要： A general rate N/(N+1) (0, G), code construction, e.g., for a magnetic recording system, allows for encoding or decoding of a dataword having N elements, N preferably being an integer multiple of eight. The dataword is divided into N/8 bytes of binary data that are encoded as a run-length limited (RLL) codeword in accordance with the general rate N/(N+1) (0, G) code construction. The general rate N/(N+1) (0, G) code construction is characterized by the constraints (d=0, G=(N/4)+1, l=N/8, r=N/8). the N/(N+1) (0 (N/4)+1, N/8, N/8) RLL codeword is constructed from the dataword in accordance with 1) pivot bits identifying code violations related to the constraints, 2) correction bits set to correct code violations, and 3) preserved elements having values not included in the code violations. The corrections by correction bits correspond to corrections of predefined code violations that limit the number of consecutive zeros received by, for example, a magnetic record channel to (N/4)+1. The codewords generated in accordance with the general rate N/(N+1) (0, G) code construction may exhibit a high transition density. The high transition density allows for more frequent timing and gain control updates, and so results in lower required channel input signal to noise ratio for a given level of magnetic recording channel performance.
摘要翻译：通常的速率N /（N + 1）（0，G），代码构造，例如用于磁记录系统，允许对具有N个元素的数据字进行编码或解码，N优选地是8的整数倍。数据字根据通用速率N /（N + 1）（0，G）码构造被划分为被编码为游程长度限制（RLL）码字的二进制数据的N / 8字节。一般速率N /（N + 1）（0，G）码结构的特征在于约束（d = 0，G =（N / 4）+1，l = N / 8，r = N / 8）。根据1）识别与约束相关的代码违例的枢轴位，从数据字构造N /（N + 1）（0（N / 4）+1，N / 8，N / 8）RLL码字，2）校正位设置为纠正代码违例，以及3）保留的元素具有不包括在代码违规中的值。校正位的校正对应于将例如由磁记录通道接收到的（N / 4）+1接收的连续零数量的预定义代码违例的校正。根据一般速率N /（N + 1）（0，G）码构造生成的码字可以表现出高转换密度。高转换密度允许更频繁的定时和增益控制更新，因此导致给定级别的磁记录通道性能所需的通道输入信噪比更低。

7. 发明授权

US06046691A Rate 16/17 (0,5) modulation code apparatus and method for partial response magnetic recording channels 失效
标题翻译：速率16/17（0,5）调制码装置和部分响应磁记录通道的方法
公开(公告)号：US06046691A
公开(公告)日：2000-04-04
申请号：US59061
申请日：1998-04-13
申请人： Pervez M. Aziz , Patrick W. Kempsey , Srinivasan Surendran
发明人： Pervez M. Aziz , Patrick W. Kempsey , Srinivasan Surendran
IPC分类号： G11B20/10 , G11B20/14 , G11B20/18 , H03M7/14 , H03M13/00 , H03M13/23 , H03M13/25 , H04L1/00 , H04L25/497 , H03M7/00
CPC分类号： H04L1/0057 , G11B20/1426 , H04L1/0041 , H04L1/0045 , G11B2020/1434 , G11B2020/1446 , G11B2020/1449
摘要： A system and method employing a rate 16/17 (0,5) code constructed in accordance with a set of pivot bits and a set of corrections for predefined code violations limits the number of consecutive zeros seen by a channel to five. The rate 16/17 (0,5) code is suitable for magnetic or similar recording media and may be employed in partial response maximum likelihood read channels. A feature of the constructed code is a high transition density which allows for more frequent timing and gain control updates, which results in lower required channel input signal to noise ratio for a given channel performance. Each constructed codeword is block encodable and block decodable, and the code construction allows for efficient circuit implementation in both an encoder and a decoder.
摘要翻译：使用根据一组枢轴位构成的速率16/17（0.5）码和用于预定义代码违规的一组校正的系统和方法将由频道看到的连续零数限制为五。速率16/17（0,5）代码适用于磁性或类似的记录介质，可用于部分响应最大似然读取通道。构造的代码的特征是高转换密度，其允许更频繁的定时和增益控制更新，这导致给定信道性能所需的信道输入信噪比更低。每个构造的码字是可编码块和块可解码的，并且代码构造允许在编码器和解码器中有效地实现电路。

8. 发明授权

US5682125A Adaptive analog transversal equalizer 失效
标题翻译：自适应模拟横向均衡器
公开(公告)号：US5682125A
公开(公告)日：1997-10-28
申请号：US536008
申请日：1995-09-29
申请人： Vadim B. Minuhin , Vladimir Kovner , Srinivasan Surendran
发明人： Vadim B. Minuhin , Vladimir Kovner , Srinivasan Surendran
IPC分类号： G11B20/10 , H03H15/00 , H03H17/00 , H03H21/00 , H04B3/06 , H04B3/14 , H04L7/02 , H04L25/03 , H04B3/04
CPC分类号： H03H21/0012 , G11B20/10009 , H04L7/0058 , H04L2025/03369 , H04L2025/03445 , H04L2025/03611
摘要： An analog, adaptive generalized transversal equalizer for use in the filtering system of a disc drive PRML read channel, the transversal equalizer employing the use of non-ideal delay elements. The filtering system comprises the equalizer connected in series with an adaptive, analog prefilter. The prefilter is comprised of a plurality of serially connected, adaptive, analog filter stages having variable transfer functions determined by adaptive parameter signals received by the filter stages. The generalized transversal equalizer comprises a plurality of serially connected, adaptive, analog low pass filters, having taps on either side of each low pass filter, a plurality of multipliers that receive signals at the tap locations of the delay circuit, and a summing circuit that receives the outputs of the multipliers. The transfer functions of the delay circuit are continuously variable in relation to adaptive parameter signals received by the delay circuit and the coefficients of multiplication are variable in relation to the adaptation process.
摘要翻译：一种用于磁盘驱动器PRML读通道的滤波系统的模拟自适应广义横向均衡器，横向均衡器采用非理想延迟元件。滤波系统包括与自适应模拟预滤波器串联连接的均衡器。预滤波器由多个串联的自适应模拟滤波器级组成，其具有由滤波器级接收的自适应参数信号确定的可变传递函数。广义横向均衡器包括多个串行连接的自适应模拟低通滤波器，每个低通滤波器的两侧具有抽头，在延迟电路的抽头位置处接收信号的多个乘法器以及一个求和电路，接收乘法器的输出。延迟电路的传递函数相对于由延迟电路接收的自适应参数信号是连续可变的，并且乘法系数相对于适应过程是可变的。

9. 发明授权

US5392171A Fully integrated programmable filters for disc drive subsystems 失效
标题翻译：用于磁盘驱动器子系统的完全集成可编程滤波器
公开(公告)号：US5392171A
公开(公告)日：1995-02-21
申请号：US165732
申请日：1993-12-10
申请人： Vladimir Kovner , Vadim B. Minuhin , Srinivasan Surendran
发明人： Vladimir Kovner , Vadim B. Minuhin , Srinivasan Surendran
IPC分类号： G11B5/012 , G11B5/02 , H03H11/04 , H03L7/089 , H03L7/093 , G11B5/09 , H03G3/00
CPC分类号： H03L7/093 , G11B5/02 , H03H11/0444 , H03H11/0472 , H03L7/0891 , G11B5/012
摘要： A disc drive system includes a plurality of subsystems. At least one of the subsystems includes a filter which is completely integrated using a synthetic integrated circuit element.
摘要翻译：磁盘驱动器系统包括多个子系统。子系统中的至少一个包括使用合成集成电路元件完全集成的滤波器。

10. 发明授权

US07688972B2 Method and system for implementing FO function in KASUMI algorithm for accelerating cryptography in GSM (global system for mobile communication)GPRS (general packet radio service)edge(enhanced data rate for GSM evolution) compliant handsets 失效
标题翻译：用于在GSM（全球移动通信系统）中加速加密的KASUMI算法中的FO功能的方法和系统用于GSM（通用分组无线电业务）边缘（用于GSM演进的增强数据速率）的手持机
公开(公告)号：US07688972B2
公开(公告)日：2010-03-30
申请号：US10923954
申请日：2004-08-23
申请人： Ruei-Shiang Suen , Srinivasan Surendran
发明人： Ruei-Shiang Suen , Srinivasan Surendran
IPC分类号： H04K1/00 , H04L9/00 , H04L9/28
CPC分类号： H04L9/0625 , H04L2209/125 , H04L2209/24 , H04L2209/80
摘要： In a wireless communication system, a method and system for implementing an FO function in a KASUMI algorithm for accelerating cryptography in GSM/GPRS/EDGE compliant handsets are provided. An efficient implementation of the FO function may comprise circuitry provided for a pipeline state machine, an FI function, a controller, a pipe register, and an XOR operation. Signals may be generated to control each round of FI processing and to indicate when each round is complete. The pipeline state machine may provide data input and subkey to the FI function for processing. A first and a second round FI processing outputs may be transferred to the pipe register. The second round output may be clocked from the pipe register to generate a portion of the FO function output and may also be XORed with a third round output of FI processing to generate the remaining portion of the FO function output.
摘要翻译：在无线通信系统中，提供了用于在GSM / GPRS / EDGE兼容手机中加速加密的KASUMI算法中实现FO功能的方法和系统。 FO功能的有效实施可以包括为流水线状态机提供的电路，FI功能，控制器，管道寄存器和XOR操作。可以生成信号以控制每轮FI处理并且指示何时每轮完成。流水线状态机可以向FI功能提供数据输入和子密钥进行处理。第一和第二轮FI处理输出可以传送到管道寄存器。第二轮输出可以从管道寄存器计时，以产生FO功能输出的一部分，并且还可以用FI处理的第三轮输出进行异或，以产生FO功能输出的剩余部分。

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