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1. 发明授权

US4866741A 3/2 Frequency divider 失效
标题翻译： 3/2分频器
公开(公告)号：US4866741A
公开(公告)日：1989-09-12
申请号：US289096
申请日：1988-12-23
申请人： Vadim B. Minuhin
发明人： Vadim B. Minuhin
IPC分类号： G11B20/14
CPC分类号： G11B20/1426
摘要： A 3/2 frequency divider employs two D-type flip-flops, an OR gate and an AND gate arranged to respond to an input signal at a frequency f to derive an output signal at a frequency 2/3 f. The frequency divider is employed in a code converter to encode or decode 1, 7, 2, 3 codes.
摘要翻译： 3/2分频器采用两个D型触发器，OR门和AND门被布置为以频率f响应输入信号以导出频率为2/3 f的输出信号。在码转换器中采用分频器对1，7，2，3码进行编码或解码。

2. 发明授权

US4813059A Readback recovery of run length limited codes 失效
标题翻译：运行长度限制代码的回读恢复
公开(公告)号：US4813059A
公开(公告)日：1989-03-14
申请号：US182264
申请日：1988-04-15
申请人： Vadim B. Minuhin , Vernon F. VonDeylen
发明人： Vadim B. Minuhin , Vernon F. VonDeylen
IPC分类号： H04N1/419 , H03M5/14 , H03M7/14 , H04B1/66
CPC分类号： H03M5/145
摘要： Run length limited codes, such as (1,7) codes are recovered with a dual channel recovery system in which the high resolution channel normally supplies the output (recovered) signal. The low resolution channel includes a detector, such as a delay device and gate, to detect a predetermined absence of transitions in the low resolution signal (which is indicative of long strings of successive zeros) to inhibit the high resolution channel from supplying the output. The result is to effectively block the high resolution channel from providing a false output.
摘要翻译：运行长度有限的代码，例如（1,7）代码用双通道恢复系统恢复，其中高分辨率通道通常提供输出（恢复）信号。低分辨率通道包括诸如延迟装置和门的检测器，以检测低分辨率信号（其表示连续零的长串）中的预定不存在转变以禁止高分辨率通道提供输出。结果是有效阻止高分辨率通道提供虚假输出。

3. 发明授权

US4760472A Dual channel readback recovery system 失效
标题翻译：双通道回读恢复系统
公开(公告)号：US4760472A
公开(公告)日：1988-07-26
申请号：US11973
申请日：1987-02-06
申请人： Vadim B. Minuhin , Robert E. Caddy, Jr.
发明人： Vadim B. Minuhin , Robert E. Caddy, Jr.
IPC分类号： G11B20/10 , G11B20/14 , G11B5/09
CPC分类号： G11B20/10 , G11B20/1426
摘要： A dual channel readback recovery circuit includes a high resolution channel and a low resolution channel and a data latch. A logical filter in one or both channels rejects signals that are followed by other signals if they are spaced apart less than the rejection time interval allowed by the code used. Polarity qualifying logic rejects signals in the channel that are not matched in polarity.
摘要翻译：双通道回读恢复电路包括高分辨率通道和低分辨率通道以及数据锁存器。如果一个或两个通道中的逻辑滤波器间隔小于所使用代码允许的拒绝时间间隔，则拒绝其他信号跟随的信号。极性限定逻辑拒绝通道中不匹配极性的信号。

4. 发明授权

US5682125A Adaptive analog transversal equalizer 失效
标题翻译：自适应模拟横向均衡器
公开(公告)号：US5682125A
公开(公告)日：1997-10-28
申请号：US536008
申请日：1995-09-29
申请人： Vadim B. Minuhin , Vladimir Kovner , Srinivasan Surendran
发明人： Vadim B. Minuhin , Vladimir Kovner , Srinivasan Surendran
IPC分类号： G11B20/10 , H03H15/00 , H03H17/00 , H03H21/00 , H04B3/06 , H04B3/14 , H04L7/02 , H04L25/03 , H04B3/04
CPC分类号： H03H21/0012 , G11B20/10009 , H04L7/0058 , H04L2025/03369 , H04L2025/03445 , H04L2025/03611
摘要： An analog, adaptive generalized transversal equalizer for use in the filtering system of a disc drive PRML read channel, the transversal equalizer employing the use of non-ideal delay elements. The filtering system comprises the equalizer connected in series with an adaptive, analog prefilter. The prefilter is comprised of a plurality of serially connected, adaptive, analog filter stages having variable transfer functions determined by adaptive parameter signals received by the filter stages. The generalized transversal equalizer comprises a plurality of serially connected, adaptive, analog low pass filters, having taps on either side of each low pass filter, a plurality of multipliers that receive signals at the tap locations of the delay circuit, and a summing circuit that receives the outputs of the multipliers. The transfer functions of the delay circuit are continuously variable in relation to adaptive parameter signals received by the delay circuit and the coefficients of multiplication are variable in relation to the adaptation process.
摘要翻译：一种用于磁盘驱动器PRML读通道的滤波系统的模拟自适应广义横向均衡器，横向均衡器采用非理想延迟元件。滤波系统包括与自适应模拟预滤波器串联连接的均衡器。预滤波器由多个串联的自适应模拟滤波器级组成，其具有由滤波器级接收的自适应参数信号确定的可变传递函数。广义横向均衡器包括多个串行连接的自适应模拟低通滤波器，每个低通滤波器的两侧具有抽头，在延迟电路的抽头位置处接收信号的多个乘法器以及一个求和电路，接收乘法器的输出。延迟电路的传递函数相对于由延迟电路接收的自适应参数信号是连续可变的，并且乘法系数相对于适应过程是可变的。

5. 发明授权

US5430768A Maximum likelihood detector for a disc drive PRML read channel 失效
标题翻译：磁盘驱动器PRML读通道的最大似然检测器
公开(公告)号：US5430768A
公开(公告)日：1995-07-04
申请号：US309870
申请日：1994-09-21
申请人： Vadim B. Minuhin , Vladimir Kovner , Steven V. Holsinger , Shafaollah Dahandeh
发明人： Vadim B. Minuhin , Vladimir Kovner , Steven V. Holsinger , Shafaollah Dahandeh
IPC分类号： G11B20/10 , H03M13/41 , H03D1/00
CPC分类号： H03M13/6343 , G11B20/10009 , H03M13/41 , H03M13/6502
摘要： A maximum likelihood detector for a disc drive in which data files are stored along tracks as a sequence of magnetically written data elements that give rise to a signal in the disc drive read chapel. The detector includes even and odd Viterbi decoders that determine the most likely even and odd subsequences of data elements from even and odd samples of the signal and a postcoder that generates the most likely sequence of bits of encoded user data from the subsequences. Each Viterbi decoder includes an analog adder and an analog subtracter for generating the sums and differences of each sample and a reference signal, a sample and hold circuit codected to the adder and subtracter to receive the sums and differences, a difference circuit that generates the difference between the contents of the sample and hold circuit and each sample, a comparator assembly that generates a two bit merge indicator signal from the output of the difference circuit and the reference signal, AND gates that transmit bits of the indicator signal to switches in the sample and hold circuit for entering the sum or difference of the sample and reference signal into the sample and hold circuit, a shift register having interstate decoders that transmit logical 1's in response to a specific nonzero bit of the merge indicator signal and an indicator bit while otherwise transmitting a logic value determined by the logic value received from a preceding stage of the shift register and a pointer for generating indicator bits for each sample for which the merge indicator signal is logical 00.
摘要翻译：用于磁盘驱动器的最大似然检测器，其中数据文件沿着磁道存储为在盘驱动器读教堂中产生信号的磁写数据元素的序列。该检测器包括偶数和奇数维特比解码器，其从信号的偶数和奇数样本确定数据元素的最可能偶数和奇数子序列;以及后编码器，其生成来自子序列的编码用户数据的最可能的位序列。每个维特比解码器包括一个模拟加法器和一个模拟减法器，用于产生每个采样和参考信号的和和差值，连接到加法器和减法器的采样和保持电路以接收和和差值，产生差值的差分电路在采样和保持电路的内容与每个采样之间，比较器组件，其从差分电路的输出和参考信号产生两位合并指示符信号，以及将指示符信号的位传送到采样中的开关的与门并且保持电路用于将采样和参考信号的和或差分输入到采样和保持电路中，移位寄存器具有响应于合并指示符信号的特定非零位而发送逻辑1的状态解码器和否则指示符位发送由从移位寄存器的前级接收的逻辑值确定的逻辑值，a 用于为合并指示符信号为逻辑00的每个样本生成指示符位的指针。

6. 发明授权

US5392171A Fully integrated programmable filters for disc drive subsystems 失效
标题翻译：用于磁盘驱动器子系统的完全集成可编程滤波器
公开(公告)号：US5392171A
公开(公告)日：1995-02-21
申请号：US165732
申请日：1993-12-10
申请人： Vladimir Kovner , Vadim B. Minuhin , Srinivasan Surendran
发明人： Vladimir Kovner , Vadim B. Minuhin , Srinivasan Surendran
IPC分类号： G11B5/012 , G11B5/02 , H03H11/04 , H03L7/089 , H03L7/093 , G11B5/09 , H03G3/00
CPC分类号： H03L7/093 , G11B5/02 , H03H11/0444 , H03H11/0472 , H03L7/0891 , G11B5/012
摘要： A disc drive system includes a plurality of subsystems. At least one of the subsystems includes a filter which is completely integrated using a synthetic integrated circuit element.
摘要翻译：磁盘驱动器系统包括多个子系统。子系统中的至少一个包括使用合成集成电路元件完全集成的滤波器。

7. 发明授权

US4875108A Phase lock loop 失效
标题翻译：锁相环
公开(公告)号：US4875108A
公开(公告)日：1989-10-17
申请号：US227216
申请日：1988-08-02
申请人： Vadim B. Minuhin , Evgeny J. Berzon , Vernon F. VonDeylen
发明人： Vadim B. Minuhin , Evgeny J. Berzon , Vernon F. VonDeylen
IPC分类号： G11B19/02 , G11B20/14 , H03L7/081 , H04N7/035
CPC分类号： H03L7/081 , G11B19/02 , G11B20/1403 , G11B20/1419 , H04N7/0352
摘要： A phase lock loop includes a phase shift apparatus to provide a plurality (i.e., four) phase-shifted clock signals from the VCO. A phase selector is responsive to a triggering signal from a one-shot multivibrator to select the one phase-shifted clock signal next following termination of the trigger signal. The one-shot is responsive to a change between the read and write mode to initiate operation of the phase selector. As a result, the initial phase error between the input signal (read pulses or write clock) and the clock signal of the phase lock loop is no more than 1/8 window.
摘要翻译：锁相环包括从VCO提供多个（即四个）相移时钟信号的相移装置。相位选择器响应来自单触发多谐振荡器的触发信号，在触发信号终止之后选择下一个相移时钟信号。一次性响应于读和写模式之间的变化，以启动相位选择器的操作。结果，输入信号（读脉冲或写时钟）与锁相环的时钟信号之间的初始相位误差不大于1/8窗口。

8. 发明授权

US4823209A 1,7,2,3 Encoding/decoding employing 3/2 frequency division 失效
标题翻译： 1,7,2,3采用3/2分频的编码/解码
公开(公告)号：US4823209A
公开(公告)日：1989-04-18
申请号：US116989
申请日：1987-11-05
申请人： Vadim B. Minuhin
发明人： Vadim B. Minuhin
IPC分类号： G11B20/14 , G11B5/09
CPC分类号： G11B20/1426
摘要： An encoding/decoding system for 1,7,2,3 codes employs an oscillator having a frequency f and dividers providing signals at frequencies equal to 1/3 f and 2/3 f. A code converter is responsive to the three signals to encode or decode data. A 3/2 frequency divider employs two D-type flip-flops, an OR gate and an AND gate arranged to respond to an input signal at a frequency f to derive an output signal at a frequency 2/3 f.

9. 发明授权

US4800295A Retriggerable monostable multivibrator 失效
标题翻译：可再触发单稳态多谐振荡器
公开(公告)号：US4800295A
公开(公告)日：1989-01-24
申请号：US174553
申请日：1988-03-29
申请人： Vadim B. Minuhin , Vernon F. Von Deylen
发明人： Vadim B. Minuhin , Vernon F. Von Deylen
IPC分类号： G11B20/10 , G11B20/14 , H03K3/10 , H03K3/033
CPC分类号： G11B20/10 , G11B20/1426
摘要： A retriggerable monostable multivibrator according to the present invention comprises a bistable device, such as S-R latch, responsive to the output of a pulse former to provide a set output. A propagation chain, comprising a plurality of serially arranged gates, propagates the latch output to form a delayed reset signal. The reset signal operates to reset the bistable latch. Gate means is connected to the true output of the latch, and to the propagation chain, to provide an output pulse for the duration of the true output and reset signal. The gates of the propagation chain are also connected to the pulse former so that the propagation of the reset signal is terminated in the event a second input pulse occurs prior to termination of the reset signal. The latch is again set and the output pulse is thereby extended by a time period equal to the predetermined time period established by the true condition of the latch, the propagation of the reset signal through the propagation chain, and the reset time of latch. Modifications describe variations of the propagation chain as including AND gates, OR gates, NOR gates and inverters.
摘要翻译：根据本发明的可再触发单稳态多谐振荡器包括响应于脉冲形成器的输出以提供置位输出的双稳态器件，例如S-R锁存器。包括多个串联布置的栅极的传播链传播锁存器输出以形成延迟复位信号。复位信号用于复位双稳态锁存器。门装置连接到锁存器和传播链的真实输出，以在真实输出和复位信号的持续时间内提供输出脉冲。传播链的栅极也连接到脉冲形成器，使得在复位信号终止之前发生第二输入脉冲的情况下，复位信号的传播被终止。再次设置锁存器，并且输出脉冲由此延长等于由锁存器的真实条件，复位信号通过传播链的传播以及锁存器复位时间建立的预定时间段的时间周期。修改描述了传播链的变化，包括与门，或门，或非门和反相器。

10. 发明授权

US5592340A Communication channel with adaptive analog transversal equalizer 失效
标题翻译：具有自适应模拟横向均衡器的通信通道
公开(公告)号：US5592340A
公开(公告)日：1997-01-07
申请号：US309912
申请日：1994-09-21
申请人： Vadim B. Minuhin , Vladimir Kovner , Srinivasan Surendran
发明人： Vadim B. Minuhin , Vladimir Kovner , Srinivasan Surendran
IPC分类号： G11B20/10 , H03H21/00 , H04L7/02 , H04L25/03 , G11B5/09 , G11B5/035
CPC分类号： H04L7/0058 , G11B20/10009 , H03H21/0012 , H04L2025/03369 , H04L2025/03445 , H04L2025/03611
摘要： An adaptive, analog filter system of a PRML [PARTIAL RESPONSE MAXIMUM LIKELIHOOD ] read channel of a disc drive comprising an adaptive, analog transversal equator connected in series with an adaptive, analog prefilter. The prefilter is comprised of a plurality of serially connected, adaptive, analog filter stages having variable transfer functions determined by adaptive parameter signals received by the filter stages. The transversal equalizer is comprised of a delay circuit, comprised of a plurality of serially connected, adaptive, analog sixth order low pass filters, that is tapped to either side of each low pass filter, a plurality of analog multipliers that receive signals at the tap locations of the delay circuit, and a summing circuit that receives the outputs of the multipliers. The transfer functions of the sixth order low pass filters are continuously variable in relation to adaptive parameter signals received by the low pass filters and the gains of the multipliers are continuously variable in relation to tap weights received by the multipliers.
摘要翻译：自适应模拟滤波器系统，包括与自适应模拟预滤波器串联连接的自适应模拟横向赤道的盘驱动器的PRML [部分响应最大似然]读通道。预滤波器由多个串联的自适应模拟滤波器级组成，其具有由滤波器级接收的自适应参数信号确定的可变传递函数。横向均衡器包括延迟电路，该延迟电路由多个串联连接的自适应模拟六阶低通滤波器组成，其被抽头到每个低通滤波器的任一侧，多个模拟乘法器在接收器处接收信号延迟电路的位置，以及接收乘法器的输出的求和电路。关于由低通滤波器接收的自适应参数信号，六阶低通滤波器的传递函数是连续可变的，并且乘法器的增益相对于乘法器接收的抽头权重是连续可变的。

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