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1. 发明申请

US20170092847A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20170092847A1
公开(公告)日：2017-03-30
申请号：US15177597
申请日：2016-06-09
申请人： Jong-Uk KIM , Jung-Moo LEE , Soon-Oh PARK , Jung-Hwan PARK , Sug-Woo JUNG
发明人： Jong-Uk KIM , Jung-Moo LEE , Soon-Oh PARK , Jung-Hwan PARK , Sug-Woo JUNG
IPC分类号： H01L43/08 , G11C11/16 , H01L27/22 , H01L43/10 , H01L43/12 , H01L43/02
CPC分类号： H01L43/08 , G11C11/161 , H01L27/228 , H01L43/02 , H01L43/10 , H01L43/12
摘要： A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.

2. 发明申请

US20130171743A1 MAGNETIC DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：磁性装置及其制造方法
公开(公告)号：US20130171743A1
公开(公告)日：2013-07-04
申请号：US13729147
申请日：2012-12-28
申请人： Jang-eun Lee , Soon-oh Park , Sang-hwan Park , Hee-ju Shin
发明人： Jang-eun Lee , Soon-oh Park , Sang-hwan Park , Hee-ju Shin
IPC分类号： H01L43/12
CPC分类号： H01L43/12 , G11C11/161 , H01L27/228
摘要： A magnetic device and a method of manufacturing the same. In the method, a lower magnetic layer, an insulation layer, and an upper magnetic layer are sequentially formed on a substrate. An upper magnetic layer pattern is formed by patterning the upper magnetic layer until an upper surface of the insulation layer is exposed. An isolation layer pattern is formed from portions of the insulation layer and the lower magnetic layer by performing an oxidation process on the exposed upper surface of the insulation layer, and an insulation layer pattern and a lower magnetic layer pattern are formed from portions of the insulation layer and the lower magnetic layer, where the isolation layer pattern is not formed.
摘要翻译：磁性装置及其制造方法。在该方法中，在基板上依次形成下磁性层，绝缘层和上磁性层。通过图案化上磁性层直到绝缘层的上表面露出来形成上部磁性层图案。通过在绝缘层的暴露的上表面上进行氧化处理，从绝缘层和下部磁性层的部分形成隔离层图案，并且绝缘层图案和下部磁性层图案由绝缘体的一部分形成层和下磁性层，其中不形成隔离层图案。

3. 发明申请

US20130017663A1 METHOD OF FORMING A PHASE CHANGE MATERIAL LAYER PATTERN AND METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE 有权
标题翻译：形成相变材料层图案的方法和制造相变存储器件的方法
公开(公告)号：US20130017663A1
公开(公告)日：2013-01-17
申请号：US13543905
申请日：2012-07-09
申请人： JEONG-HEE PARK , SOON-OH PARK , JUNG-HWAN PARK , JIN-HO OH
发明人： JEONG-HEE PARK , SOON-OH PARK , JUNG-HWAN PARK , JIN-HO OH
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/141 , H01L45/1683
摘要： A method of forming a phase change material layer pattern includes forming a phase change material layer partially filling an opening through an insulating interlayer. A plasma treatment process is performed on the phase change material layer to remove an oxide layer on a surface of the phase change material layer. A heat treatment process is performed on the phase change material layer to remove a void or a seam in the phase change material layer, sufficiently filling the opening.
摘要翻译：形成相变材料层图案的方法包括：通过绝缘中间层形成部分填充开口的相变材料层。在相变材料层上进行等离子体处理工艺以去除相变材料层的表面上的氧化物层。在相变材料层上进行热处理工艺以去除相变材料层中的空隙或接缝，充分填充开口。

4. 发明授权

US08320170B2 Multi-bit phase change memory devices 有权
标题翻译：多位相变存储器件
公开(公告)号：US08320170B2
公开(公告)日：2012-11-27
申请号：US12656716
申请日：2010-02-16
申请人： Young-nam Hwang , Soon-oh Park , Hong-sik Jeong , Gi-tae Jeong
发明人： Young-nam Hwang , Soon-oh Park , Hong-sik Jeong , Gi-tae Jeong
IPC分类号： G11C11/00
CPC分类号： H01L45/065 , G11C11/5678 , G11C13/0004 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A multi-bit phase change memory device including a phase change material having a plurality of crystalline phases. A non-volatile multi-bit phase change memory device may include a phase change material in a storage node, wherein the phase change material includes a binary or ternary compound sequentially having at least three crystalline phases having different resistance values according to an increase of temperature of the phase change material.
摘要翻译：一种多位相变存储器件，包括具有多个结晶相的相变材料。非易失性多位相变存储器件可以包括存储节点中的相变材料，其中相变材料包括依次具有至少三个根据温度升高的不同电阻值的晶相的二元或三元化合物的相变材料。

5. 发明授权

US08187918B2 Methods of forming multi-level cell of semiconductor memory 有权
标题翻译：形成半导体存储器多级单元的方法
公开(公告)号：US08187918B2
公开(公告)日：2012-05-29
申请号：US12587772
申请日：2009-10-13
申请人： Gyu-Hwan Oh , Hyeung-Geun An , Soon-Oh Park , Dong-Ho Ahn , Young-Lim Park
发明人： Gyu-Hwan Oh , Hyeung-Geun An , Soon-Oh Park , Dong-Ho Ahn , Young-Lim Park
IPC分类号： H01L21/06
CPC分类号： H01L45/141 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/1666 , H01L45/1683
摘要： Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.
摘要翻译：提供了一种形成半导体存储单元的方法，其中为了在存储单元中存储两个或更多个数据，三个或更多个底部电极触点（BEC）和相变材料（GST）在单个存储单元上具有并联结构接触插头（CP）和设定电阻根据三个或更多个底部电极触点的厚度（S），长度（L）或电阻率（＆rgr）而改变，因此复位电阻和三种不同的设定电阻使数据不能在设置和复位状态下存储。此外，形成其中三个或更多个相变材料（GST）在单个底部电极接触上具有平行结构的存储单元的方法，并且相变材料根据组成比或类型具有不同的设定电阻，因此可以实现四个或更多个不同的电阻。

6. 发明申请

US20090101881A1 SEMICONDUCTOR DEVICES HAVING PHASE CHANGE MEMORY CELLS, ELECTRONIC SYSTEMS EMPLOYING THE SAME AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有相变记忆体的半导体器件，使用其的电子系统及其制造方法
公开(公告)号：US20090101881A1
公开(公告)日：2009-04-23
申请号：US12338814
申请日：2008-12-18
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L45/00
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.
摘要翻译：在一个实施例中，相变存储器件具有防止存储器单元污染或氧化的氧化阻挡层及其制造方法。在一个实施例中，半导体存储器件包括覆盖半导体衬底的成型层。模制层具有从其顶表面垂直延伸的突出部分。该装置还包括与突出部分相邻的相变材料图案和与相变材料图案电连接的下部电极。

7. 发明申请

US20070243659A1 PHASE-CHANGEABLE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070243659A1
公开(公告)日：2007-10-18
申请号：US11733131
申请日：2007-04-09
申请人： Hee-Ju SHIN , Jong-Chan SHIN , Soon-Oh PARK , Hyeong-Geun AN , Han-Bong KO
发明人： Hee-Ju SHIN , Jong-Chan SHIN , Soon-Oh PARK , Hyeong-Geun AN , Han-Bong KO
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer is etched to be a first insulating layer pattern having a first opening exposing the first pad. A first plug is formed in the first opening. The first insulating layer pattern where the first plug is formed is etched to be a second insulating layer pattern having a second opening exposing the lower electrode. A second plug including a phase-changeable material is formed in the second opening. A conductive wire and an upper electrode are formed on the first plug and the second plug, respectively.
摘要翻译：在半导体存储器件及其制造方法中，在具有设置有第一焊盘的逻辑区域的衬底上形成绝缘层，并且随后设置有第二焊盘和下电极的单元区域。绝缘层被蚀刻成具有第一开口的第一绝缘层图案，该第一开口露出第一焊盘。第一插头形成在第一开口中。将形成有第一插塞的第一绝缘层图案蚀刻成具有暴露下电极的第二开口的第二绝缘层图案。包括相变材料的第二插头形成在第二开口中。导线和上电极分别形成在第一插头和第二插头上。

8. 发明申请

US20050263829A1 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US20050263829A1
公开(公告)日：2005-12-01
申请号：US11139283
申请日：2005-05-27
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L21/00 , H01L21/336 , H01L27/24 , H01L29/00 , H01L29/78
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.
摘要翻译：在一个实施例中，相变存储器件具有防止存储器单元污染或氧化的氧化阻挡层及其制造方法。在一个实施例中，半导体存储器件包括覆盖半导体衬底的成型层。模制层具有从其顶表面垂直延伸的突出部分。该装置还包括与突出部分相邻的相变材料图案和与相变材料图案电连接的下部电极。

9. 发明申请

US20170271581A1 SEMICONDUCTOR MEMORY DEVICES 审中-公开
公开(公告)号：US20170271581A1
公开(公告)日：2017-09-21
申请号：US15438938
申请日：2017-02-22
申请人： Dong-Jun SEONG , Sung-Ho EUN , Soon-Oh PARK
发明人： Dong-Jun SEONG , Sung-Ho EUN , Soon-Oh PARK
IPC分类号： H01L45/00 , H01L43/12 , H01L27/22 , H01L27/24 , H01L43/02 , H01L43/08
CPC分类号： H01L45/06 , H01L27/224 , H01L27/2409 , H01L27/2427 , H01L27/2481 , H01L43/02 , H01L43/08 , H01L43/12 , H01L45/08 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/1675 , H01L45/1683
摘要： A semiconductor memory device includes first conductive lines extending in a first direction on a substrate, second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points, a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element, and an insulation pattern insulating the first and the second conductive lines and the cell structures from one another.

10. 发明申请

US20110284815A1 PHASE-CHANGE MEMORY DEVICES HAVING STRESS RELIEF BUFFERS 审中-公开
标题翻译：具有应力消除缓冲器的相变存储器件
公开(公告)号：US20110284815A1
公开(公告)日：2011-11-24
申请号：US13070648
申请日：2011-03-24
申请人： Ik-soo Kim , Soon-oh Park , Dong-ho Ahn , Sung-lae Cho , Dae-hong Ko , Hyun-chul Sohn , Ki-hoon Do , Mann-ho Cho
发明人： Ik-soo Kim , Soon-oh Park , Dong-ho Ahn , Sung-lae Cho , Dae-hong Ko , Hyun-chul Sohn , Ki-hoon Do , Mann-ho Cho
IPC分类号： H01L47/00
CPC分类号： H01L45/12 , H01L45/06 , H01L45/144
摘要： A memory device includes a substrate and a memory cell including a first electrode on the substrate, a phase-change material region on the first electrode and a second electrode on the phase-change material region opposite the first electrode. The memory device further includes a stress relief buffer adjacent a sidewall of the phase-change material region between the first and second electrodes. In some embodiments, the stress relief buffer includes a stress relief region contacting the sidewall of the phase-change material region. In further embodiments, the stress relief buffer includes a void adjacent the sidewall of the phase-change material region.
摘要翻译：存储器件包括衬底和存储单元，该存储单元包括衬底上的第一电极，第一电极上的相变材料区域和与第一电极相对的相变材料区域上的第二电极。存储器件还包括与第一和第二电极之间的相变材料区域的侧壁相邻的应力释放缓冲器。在一些实施例中，应力消除缓冲器包括接触相变材料区域的侧壁的应力消除区域。在另外的实施例中，应力消除缓冲器包括邻近相变材料区域的侧壁的空隙。

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