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1. 发明授权

US09349155B2 Computing apparatus and method using X-Y stack memory 有权
标题翻译：使用X-Y堆栈存储器的计算设备和方法
公开(公告)号：US09349155B2
公开(公告)日：2016-05-24
申请号：US13171772
申请日：2011-06-29
申请人： Soo-Jung Ryu , Sung-Bae Park , Woong Seo , Young-Chul Cho , Jeong-Wook Kim , Moo-Kyoung Chung , Ho-Young Kim
发明人： Soo-Jung Ryu , Sung-Bae Park , Woong Seo , Young-Chul Cho , Jeong-Wook Kim , Moo-Kyoung Chung , Ho-Young Kim
IPC分类号： G06T1/60 , G06F13/00 , G06F12/02
CPC分类号： G06T1/60
摘要： A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis.
摘要翻译：提供了一种计算装置。计算装置包括存储单元，其被配置为具有被定义为具有至少两个轴的多维空间的地址空间，以及存储器访问单元，其被配置为包括存储指向与第一轴对应的行的第一指针的第一指针寄存器，以及存储指向对应于第二轴的列的第二指针的第二指针寄存器。

2. 发明授权

US08516231B2 Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus 有权
标题翻译：包含中断处理装置的等模型处理器和处理器的中断处理装置和方法
公开(公告)号：US08516231B2
公开(公告)日：2013-08-20
申请号：US12695266
申请日：2010-01-28
申请人： Il-hyun Park , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger
发明人： Il-hyun Park , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger
IPC分类号： G06F15/00 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3836 , G06F9/327
摘要： An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency.
摘要翻译：提供了一种用于等模型处理器的中断支持确定装置和方法，以及包括中断支持确定装置的处理器。中断支持确定装置确定输入到处理器解码器的指令是否是多等待时间指令，如果指令是多等待时间指令，则将指令的当前等待时间与剩余延迟进行比较，并将当前等待时间更新为剩余延迟，如果当前的延迟大于剩余的延迟。

3. 发明申请

US20130067203A1 PROCESSING DEVICE AND A SWIZZLE PATTERN GENERATOR 审中-公开
标题翻译：处理装置和SWIZLE模式发生器
公开(公告)号：US20130067203A1
公开(公告)日：2013-03-14
申请号：US13618309
申请日：2012-09-14
申请人： Moo-Kyoung Chung , Woong Seo , Ho-Young Kim , Soo-Jung Ryu , Dong-Hoon Yoo , Jin-Seok Lee , Yeon-Gon Cho , Chang-Moo Kim , Seung-Hun Jin
发明人： Moo-Kyoung Chung , Woong Seo , Ho-Young Kim , Soo-Jung Ryu , Dong-Hoon Yoo , Jin-Seok Lee , Yeon-Gon Cho , Chang-Moo Kim , Seung-Hun Jin
IPC分类号： G06F9/302
CPC分类号： G06F9/30032 , G06F9/30036
摘要： A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.
摘要翻译：提供了一种旋转模式发生器，以减少由于在矢量处理中执行旋转指令而导致的开销。旋转图案生成器被配置为提供关于至少一个向量寄存器或向量处理单元的数据集的旋转图案。旋转图案发生器可以是可重构的，以产生用于不同矢量操作的各种旋转图案。

4. 发明申请

US20120158394A1 SIMULATION APPARATUS AND METHOD FOR MULTICORE SYSTEM 有权
标题翻译：模拟装置及其制作方法
公开(公告)号：US20120158394A1
公开(公告)日：2012-06-21
申请号：US13171017
申请日：2011-06-28
申请人： Young Chul Cho , Soo-Jung Ryu , Moo-Kyoung Chung , Ho-Young Kim , Woong Seo
发明人： Young Chul Cho , Soo-Jung Ryu , Moo-Kyoung Chung , Ho-Young Kim , Woong Seo
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5022 , G06F17/5031 , G06F2217/84
摘要： A simulation apparatus and method for a multicore system are provided. The simulation apparatus may prevent the occurrence of a data collision during the communication between modules and may reduce the overhead generated during simulation. The simulation apparatus may select a plurality of modules to be synchronized in terms of function execution timing based on timing information and may configure a multicore system architecture model using the selected modules. The simulation apparatus may acquire function execution timing information of the modules, control the execution of functions by the modules based on the acquired function execution timing information, and output the results of the control of the execution of functions by the modules.
摘要翻译：提供了一种用于多核系统的模拟装置和方法。模拟装置可以防止在模块之间的通信期间发生数据冲突，并且可以减少模拟期间产生的开销。模拟装置可以基于定时信息来选择要在功能执行定时上同步的多个模块，并且可以使用所选择的模块来配置多核系统体系结构模型。模拟装置可以获取模块的功能执行定时信息，基于所获取的功能执行定时信息控制模块的功能的执行，并且输出模块执行功能的控制结果。

5. 发明申请

US20110202704A1 MEMORY CONTROLLER, METHOD OF CONTROLLING MEMORY ACCESS, AND COMPUTING APPARATUS INCORPORATING MEMORY CONTROLLER 有权
标题翻译：存储器控制器，控制存储器访问的方法以及计算机存储器控制器
公开(公告)号：US20110202704A1
公开(公告)日：2011-08-18
申请号：US13006382
申请日：2011-01-13
申请人： Woong Seo , Soo-Jung Ryu , Yoon-Jin Kim , Young-Chul Cho , II-Hyun Park , Tae-Wook Oh
发明人： Woong Seo , Soo-Jung Ryu , Yoon-Jin Kim , Young-Chul Cho , II-Hyun Park , Tae-Wook Oh
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , Y02D10/14
摘要： A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data buffer by accessing the memory in an aligned word unit and output, in response to a request for an unaligned memory access by the processor, requested data by extracting the request data from the data buffer.
摘要翻译：提供一种用于访问多存储体存储器的计算装置。计算装置包括处理器，存储器和存储器控制器，其被配置为通过以对准的字单元访问存储器并且响应于处理器对未对齐的存储器访问的请求而输出来存储数据在数据缓冲器中数据通过从数据缓冲器提取请求数据。

6. 发明申请

US20100174885A1 RECONFIGURABLE PROCESSOR AND OPERATING METHOD OF THE SAME 有权
标题翻译：可重构加工器及其操作方法
公开(公告)号：US20100174885A1
公开(公告)日：2010-07-08
申请号：US12563350
申请日：2009-09-21
申请人： Il-hyun PARK , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger , Woon Seo
发明人： Il-hyun PARK , Soo-jung Ryu , Dong-hoon Yoo , Yeon-gon Cho , Bernhard Egger , Woon Seo
IPC分类号： G06F15/76 , G06F9/00
CPC分类号： G06F15/7867 , G06F9/30072 , Y02D10/12 , Y02D10/13
摘要： Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory including configuration information about an operation of a function unit, and a distributed routing configuration memory including configuration information about routing. The distributed operation configuration memory may be activated according to a predicate signal.
摘要翻译：提供了一种可重构处理器及其操作方法。可重构处理器可以使用分配给每个操作单元的配置存储器。分布式配置存储器可以被分成包括关于功能单元的操作的配置信息的分布式操作配置存储器，以及包括关于路由的配置信息的分布式路由配置存储器。可以根据谓词信号激活分布式操作配置存储器。

7. 发明授权

US07590831B2 Loop accelerator and data processing system having the same 有权
标题翻译：循环加速器和数据处理系统具有相同的功能
公开(公告)号：US07590831B2
公开(公告)日：2009-09-15
申请号：US11514889
申请日：2006-09-05
申请人： Soo-jung Ryu , Jeong-wook Kim , Suk-jin Kim , Hong-Seok Kim , Jun-jin Kong
发明人： Soo-jung Ryu , Jeong-wook Kim , Suk-jin Kim , Hong-Seok Kim , Jun-jin Kong
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/3877 , G06F9/3897 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a central register file which transmits data between the processor core and the loop accelerator. The loop accelerator includes a plurality of processing elements (PEs) each of which performs an operation on each word to execute the program, a configuration memory which stores configuration bits indicating operations, states, etc. of the PEs, and a plurality of context memories, installed in a column or row direction of the PEs, which transmit the configuration bits along a direction toward which the PEs are arrayed. Thus, a connection structure between the configuration memory and the PEs can be simplified to easily modify a structure of the loop accelerator so as to extend the loop accelerator.
摘要翻译：提供了一种环路加速器和具有环路加速器的数据处理系统。数据处理系统包括执行程序的循环部分的循环加速器，处理除循环部分之外的程序的剩余部分的处理器核心以及在处理器核心和循环加速器之间传送数据的中央寄存器文件。环路加速器包括多个处理元件（PE），每个处理元件（PE）对每个字执行操作以执行程序;配置存储器，其存储指示PE的操作，状态等的配置位，以及多个上下文存储器安装在PE的列或行方向上，其沿着PE排列的方向传送配置位。因此，可以简化配置存储器和PE之间的连接结构，以容易地修改循环加速器的结构，以便扩展循环加速器。

8. 发明授权

US07529917B2 Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array 有权
标题翻译：在可重构粗粒度阵列中循环处理中的中断处理方法和装置
公开(公告)号：US07529917B2
公开(公告)日：2009-05-05
申请号：US11519858
申请日：2006-09-13
申请人： Soo Jung Ryu , Jeong Wook Kim , Dong-Hoon Yoo , Hee Seok Kim
发明人： Soo Jung Ryu , Jeong Wook Kim , Dong-Hoon Yoo , Hee Seok Kim
IPC分类号： G06F9/00
CPC分类号： G06F9/4812
摘要： A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while executing the sub-loop in the coarse grained array, the interrupt request is processed after the executing of the sub-loop is completed.
摘要翻译：一种包括包括多个功能单元和多个寄存器文件的粗粒度阵列的处理器，其中由粗粒度阵列执行的循环被分割成多个子循环，并且当执行中断请求时发生中断请求在粗粒子数组中的子循环，中断请求在子循环执行完成后被处理。

9. 发明授权

US09141579B2 Apparatus and method for routing data among multiple cores 有权
标题翻译：用于在多个核之间路由数据的装置和方法
公开(公告)号：US09141579B2
公开(公告)日：2015-09-22
申请号：US13033728
申请日：2011-02-24
申请人： Yeon-Gon Cho , Yen-Jo Han , Soo-Jung Ryu , Jae-Young Kim , Woong Seo , Hee-Jun Shim , Jin-Seok Lee
发明人： Yeon-Gon Cho , Yen-Jo Han , Soo-Jung Ryu , Jae-Young Kim , Woong Seo , Hee-Jun Shim , Jin-Seok Lee
IPC分类号： G06F15/173 , G06F12/08
CPC分类号： G06F15/17343 , G06F12/0806
摘要： An apparatus and method for routing data among multicores that is capable of reconfiguring the connection among the multicores are provided. The apparatus includes a configuration information generating unit and at least one switching unit. The configuration information generating unit is configured to generate configuration information that indicates a local network connection among the multicores based on a program counter received from each of the multicores. The at least one switching unit is configured to change a data transfer path among the multicores based on the configuration information.
摘要翻译：提供了一种用于在能够重新配置多核间的连接的多核之间路由数据的装置和方法。该装置包括配置信息生成单元和至少一个切换单元。配置信息生成单元被配置为基于从每个多个多个接收的程序计数器生成指示多个多媒体之间的本地网络连接的配置信息。所述至少一个切换单元被配置为基于所述配置信息来改变所述多个核心之间的数据传输路径。

10. 发明授权

US08555097B2 Reconfigurable processor with pointers to configuration information and entry in NOP register at respective cycle to deactivate configuration memory for reduced power consumption 有权
标题翻译：可配置处理器，具有指向配置信息的指针，并在各个周期的NOP寄存器中输入，以停用配置存储器以降低功耗
公开(公告)号：US08555097B2
公开(公告)日：2013-10-08
申请号：US12609920
申请日：2009-10-30
申请人： Bernhard Egger , Soo-jung Ryu , Dong-hoon Yoo
发明人： Bernhard Egger , Soo-jung Ryu , Dong-hoon Yoo
IPC分类号： G06F1/32
CPC分类号： G06F9/30076 , G06F1/3203 , G06F1/324 , G06F1/3275 , G06F9/38 , G06F9/3897 , G06F15/7867 , Y02D10/126 , Y02D10/14
摘要： Described herein is a reconfigurable processor which uses a distributed configuration memory structure and an operation method thereof in which power consumption is reduced. A processing unit which configures the reconfigurable processor includes a functional unit, a distributed configuration memory, a no-operation (NOP) register, and a controller. The NOP register stores information which represents whether or not a NOP operation is performed at each clock cycle. The controller controls to deactivate the distributed configuration memory at a clock cycle at which a NOP operation is performed.
摘要翻译：这里描述的是使用其中功耗降低的分布式配置存储器结构及其操作方法的可重构处理器。配置可重构处理器的处理单元包括功能单元，分布式配置存储器，无操作（NOP）寄存器和控制器。 NOP寄存器存储表示在每个时钟周期是否执行NOP操作的信息。控制器控制在执行NOP操作的时钟周期停用分布式配置存储器。

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