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1. 发明授权

US07590831B2 Loop accelerator and data processing system having the same 有权
标题翻译：循环加速器和数据处理系统具有相同的功能
公开(公告)号：US07590831B2
公开(公告)日：2009-09-15
申请号：US11514889
申请日：2006-09-05
申请人： Soo-jung Ryu , Jeong-wook Kim , Suk-jin Kim , Hong-Seok Kim , Jun-jin Kong
发明人： Soo-jung Ryu , Jeong-wook Kim , Suk-jin Kim , Hong-Seok Kim , Jun-jin Kong
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/3877 , G06F9/3897 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a central register file which transmits data between the processor core and the loop accelerator. The loop accelerator includes a plurality of processing elements (PEs) each of which performs an operation on each word to execute the program, a configuration memory which stores configuration bits indicating operations, states, etc. of the PEs, and a plurality of context memories, installed in a column or row direction of the PEs, which transmit the configuration bits along a direction toward which the PEs are arrayed. Thus, a connection structure between the configuration memory and the PEs can be simplified to easily modify a structure of the loop accelerator so as to extend the loop accelerator.
摘要翻译：提供了一种环路加速器和具有环路加速器的数据处理系统。数据处理系统包括执行程序的循环部分的循环加速器，处理除循环部分之外的程序的剩余部分的处理器核心以及在处理器核心和循环加速器之间传送数据的中央寄存器文件。环路加速器包括多个处理元件（PE），每个处理元件（PE）对每个字执行操作以执行程序;配置存储器，其存储指示PE的操作，状态等的配置位，以及多个上下文存储器安装在PE的列或行方向上，其沿着PE排列的方向传送配置位。因此，可以简化配置存储器和PE之间的连接结构，以容易地修改循环加速器的结构，以便扩展循环加速器。

2. 发明申请

US20070157009A1 Loop accelerator and data processing system having the same 有权
标题翻译：循环加速器和数据处理系统具有相同的功能
公开(公告)号：US20070157009A1
公开(公告)日：2007-07-05
申请号：US11514889
申请日：2006-09-05
申请人： Soo-jung Ryu , Jeong-wook Kim , Suk-jin Kim , Hong-seok Kim , Jun-jin Kong
发明人： Soo-jung Ryu , Jeong-wook Kim , Suk-jin Kim , Hong-seok Kim , Jun-jin Kong
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/3877 , G06F9/3897 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a central register file which transmits data between the processor core and the loop accelerator. The loop accelerator includes a plurality of processing elements (PEs) each of which performs an operation on each word to execute the program, a configuration memory which stores configuration bits indicating operations, states, etc. of the PEs, and a plurality of context memories, installed in a column or row direction of the PEs, which transmit the configuration bits along a direction toward which the PEs are arrayed. Thus, a connection structure between the configuration memory and the PEs can be simplified to easily modify a structure of the loop accelerator so as to extend the loop accelerator.
摘要翻译：提供了一种环路加速器和具有环路加速器的数据处理系统。数据处理系统包括执行程序的循环部分的循环加速器，处理除循环部分之外的程序的剩余部分的处理器核心以及在处理器核心和循环加速器之间传送数据的中央寄存器文件。环路加速器包括多个处理元件（PE），每个处理元件（PE）对每个字执行操作以执行程序;配置存储器，其存储指示PE的操作，状态等的配置位，以及多个上下文存储器安装在PE的列或行方向上，其沿着PE排列的方向传送配置位。因此，可以简化配置存储器和PE之间的连接结构，以容易地修改循环加速器的结构，以便扩展循环加速器。

3. 发明授权

US06799296B2 Viterbi detector for optical disk system 失效
标题翻译：维特比检测器用于光盘系统
公开(公告)号：US06799296B2
公开(公告)日：2004-09-28
申请号：US09985122
申请日：2001-11-01
申请人： Jun-jin Kong , Sung-han Choi , Jae-wook Lee
发明人： Jun-jin Kong , Sung-han Choi , Jae-wook Lee
IPC分类号： H03M1300
CPC分类号： H03M13/6343 , G11B20/10009 , H03M13/3961 , H03M13/41 , H03M13/4107
摘要： A high speed Viterbi detector for an optical disk system, includes a frequency dividing unit for generating an auxiliary clock at one-third of the main clock frequency, a branch metric calculation unit for calculating each of a plurality of branch metrics, a serial-to-parallel converting unit for outputting each of the branch metrics at the main clock frequency in units of 3 state bits, an addition/comparison/selection unit for adding the branch metrics and previously stored state metrics and for comparing the addition results to select and output the minimum of the addition results as a new state metric, and for outputting a corresponding path selection signal, at the auxiliary clock frequency, a path memory for storing the path selection signal and for outputting parallel data corresponding to the path selection signal, at the auxiliary clock frequency, and a parallel-to-serial converting unit for converting the path memory output into serial data.
摘要翻译：一种用于光盘系统的高速维特比检测器，包括用于产生主时钟频率三分之一的辅助时钟的分频单元，用于计算多个分支度量中的每一个的分支量度计算单元，平行转换单元，用于以3个状态位为单位输出主时钟频率的每个分支度量，用于添加分支度量和先前存储的状态度量的加法/比较/选择单元，并用于比较加法结果以选择和输出将附加结果的最小值作为新的状态度量，并且在辅助时钟频率处输出用于存储路径选择信号并用于输出与路径选择信号相对应的并行数据的路径存储器的相应路径选择信号，辅助时钟频率以及用于将路径存储器输出转换为串行数据的并行到串行转换单元。

4. 发明授权

US6029268A Quality calculator apparatus for use with Viterbi-decoded data using zero-state metrics 失效
标题翻译：使用零状态度量的维特比解码数据使用的质量计算器装置
公开(公告)号：US6029268A
公开(公告)日：2000-02-22
申请号：US839
申请日：1997-12-30
申请人： Jun-jin Kong , Sung-han Choi
发明人： Jun-jin Kong , Sung-han Choi
IPC分类号： H04L29/14 , H03M13/23 , H03M13/35 , H03M13/41 , G06F11/10
CPC分类号： H03M13/6569 , H03M13/35 , H03M13/4107 , H03M13/413
摘要： A quality calculator apparatus for Viterbi-decoded data using zero-state metrics. The quality calculator for the Viterbi-decoded data includes: a Viterbi decoder which outputs zero-state metrics of input demodulated data according to the four possible transmission rates of FULL, HALF, QUARTER and 1/8; a register which stores respective zero-state metrics output from the Viterbi decoder; and a quality evaluation unit which reads the zero-state metrics stored in the register to evaluate the Viterbi-decoded data based on the zero-state metrics and which determines the actual transmission rate to be the one among the possible transmission rates which has the least zero-state metrics. The zero-state metrics of the demodulated data input to the Viterbi decoder are used as a quality evaluation parameter so that the quality evaluation can be correctly achieved to avoid errors in determining of the transmission rate, as compared to a quality calculator using a bit error ratio as the quality evaluation parameter.
摘要翻译：一种使用零状态度量的维特比解码数据的质量计算器装置。用于维特比解码数据的质量计算器包括：维特比解码器，其根据FULL，HALF，QUARTER和+ E，fra 1/8 + EE的四种可能的传输速率输出输入解调数据的零状态度量; 存储从维特比解码器输出的相应的零状态度量的寄存器; 以及质量评估单元，其读取存储在所述寄存器中的零状态度量，以基于所述零状态量度来评估所述维特比解码数据，并且将所述实际传输速率确定为所述可能传输速率中的最小传输速率零状态指标。将输入到维特比解码器的解调数据的零状态量度用作质量评估参数，以便与使用位错误的质量计算器相比，可以正确地实现质量评估以避免确定传输速率的错误比例作为质量评估参数。

5. 发明授权

US5881075A Viterbi decoder 失效
标题翻译：维特比解码器
公开(公告)号：US5881075A
公开(公告)日：1999-03-09
申请号：US814828
申请日：1997-03-11
申请人： Jun-jin Kong , Yong-woo Park
发明人： Jun-jin Kong , Yong-woo Park
IPC分类号： H03M13/23 , H03M13/41 , G06F11/10
CPC分类号： H03M13/3961 , H03M13/4107
摘要： A Viterbi decoder which operates a plurality of states at one time to thereby decode a plurality of channels at an increased speed. The decoder includes a branch metric calculating unit which receives convolutional data and calculates a plurality of branch metrics. A branch metric allocating unit allocates the plurality of branch metrics as even and odd branch metrics. A state metric storing unit stores a current state metric and allocates a plurality of state metrics as even and odd state metrics. First and second add-compare-select (ACS) units perform addition, comparison, and selection on the even branch and state metrics, and select paths having optimum distances. Third and fourth ACS units perform addition, comparison, and selection on the odd branch and state metrics, and select paths having optimum distances. A path tracing logic unit traces the path selection information selected in the first through fourth ACS units, and outputs decoded data. A path storing unit stores a path selection signal generated and selected in the path selection information controller.
摘要翻译：一种维特比解码器，其一次操作多个状态，从而以增加的速度解码多个信道。解码器包括分支度量计算单元，其接收卷积数据并计算多个分支度量。分支度量分配单元将多个分支度量分配为偶数和奇数分支度量。状态度量存储单元存储当前状态度量，并且将多个状态度量分配为偶数和奇数状态度量。第一和第二加 - 比选择（ACS）单元对偶分支和状态度量进行加法，比较和选择，并选择具有最佳距离的路径。第三和第四ACS单元对奇数分支和状态度量执行加法，比较和选择，并选择具有最佳距离的路径。路径跟踪逻辑单元跟踪在第一至第四ACS单元中选择的路径选择信息，并输出解码数据。路径存储单元存储在路径选择信息控制器中生成和选择的路径选择信号。

6. 发明授权

US09524208B2 Memory controller operating method and memory controller 有权
标题翻译：内存控制器操作方法和内存控制器
公开(公告)号：US09524208B2
公开(公告)日：2016-12-20
申请号：US14322404
申请日：2014-07-02
申请人： Kyung-Jin Kim , Ung-Hwan Kim , Jun-jin Kong , Nam-Shik Kim
发明人： Kyung-Jin Kim , Ung-Hwan Kim , Jun-jin Kong , Nam-Shik Kim
IPC分类号： G06F11/10 , H03M13/11 , H03M13/29 , H03M13/37 , H03M13/41 , H03M13/45 , H03M13/00 , G11C29/52 , H03M13/39
CPC分类号： G06F11/1048 , G06F11/1012 , G06F11/1068 , G11C29/52 , H03M13/1105 , H03M13/1111 , H03M13/2927 , H03M13/2957 , H03M13/2975 , H03M13/3707 , H03M13/3738 , H03M13/3746 , H03M13/3927 , H03M13/41 , H03M13/45 , H03M13/458 , H03M13/6513
摘要： A method of operating a memory controller includes; receiving hard decision data and first soft decision data from a non-volatile memory device, performing a first ECC decoding operation using the hard decision data and the first soft decision data: and then determining a second soft decision read voltage or reclaim operation of the non-volatile memory device based on the number of iteration operation of the first ECC (error correction code).
摘要翻译：操作存储器控制器的方法包括：从非易失性存储设备接收硬判决数据和第一软判决数据，使用硬判决数据和第一软判决数据执行第一ECC解码操作;然后确定第二软判决读电压或回收非非易失性存储器基于第一ECC的迭代操作次数（纠错码）的非易失性存储装置。

7. 发明申请

US20120216096A1 Memory Device and Memory System 有权
标题翻译：存储器和存储器系统
公开(公告)号：US20120216096A1
公开(公告)日：2012-08-23
申请号：US13396791
申请日：2012-02-15
申请人： Man-keun Seo , Jun-jin Kong , Kyoung-Lae Cho
发明人： Man-keun Seo , Jun-jin Kong , Kyoung-Lae Cho
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2906 , G06F11/1012 , G06F11/1044 , H03M7/30 , H03M13/05 , H03M13/6312
摘要： A memory device and a memory system, the memory system including a data compressor for generating compressed data by compressing program data in a first unit, and an error correction block generator for dividing the compressed data in a second unit to obtain a plurality of pieces of normal data, and generating error correction blocks for correcting errors of the plurality of pieces of normal data, wherein each of the error correction blocks comprises the normal data, invalid data having a size corresponding to the size of the normal data, and parities for the normal data and the invalid data.
摘要翻译：存储器装置和存储器系统，所述存储器系统包括用于通过压缩第一单元中的程序数据产生压缩数据的数据压缩器，以及用于在第二单元中分割压缩数据的纠错块发生器，以获得多个正常数据和生成用于校正多条正常数据的错误的纠错块，其中每个纠错块包括正常数据，具有与正常数据的大小相对应的大小的无效数据，以及用于正常数据和无效数据。

8. 发明申请

US20070094563A1 Method and apparatus for controlling error using reserved bits 审中-公开
标题翻译：使用保留位控制错误的方法和装置
公开(公告)号：US20070094563A1
公开(公告)日：2007-04-26
申请号：US11518307
申请日：2006-09-11
申请人： Hae-sik Kim , Jun-jin Kong , Jae-ho Roh
发明人： Hae-sik Kim , Jun-jin Kong , Jae-ho Roh
IPC分类号： H04L1/00 , H03M13/00 , G08C25/00 , G06F11/00 , G06F11/30
CPC分类号： H04L1/20 , H04L1/0009 , H04L1/0045 , H04L1/208
摘要： An apparatus for controlling an error using reserved bits including a mask indicator a pre-decoder and a decoder. The mask indicator is operable to provide mask data. The pre-decoder is operable to mask reserved bits of received data using the mask data. The decoder is operable to decode the pre-decoded received data.
摘要翻译：一种使用包括掩码指示符，预解码器和解码器的保留位来控制错误的装置。掩模指示器可操作以提供掩模数据。预解码器可操作以使用掩码数据来屏蔽接收数据的保留位。解码器可操作以对预解码的接收数据进行解码。

9. 发明授权

US09128812B2 Semiconductor storage device, system, and method 有权
标题翻译：半导体存储装置，系统和方法
公开(公告)号：US09128812B2
公开(公告)日：2015-09-08
申请号：US13610917
申请日：2012-09-12
申请人： Chang-kyu Seol , Jun-jin Kong , Hong-rak Son
发明人： Chang-kyu Seol , Jun-jin Kong , Hong-rak Son
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G11C7/04 , G11C16/0483 , G11C16/26 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/52 , G11C2029/0411
摘要： A semiconductor storage system includes: a difference determining circuit configured to determine a difference between the number of first state values of sample data written to a memory and the number of first state values of read data read from the memory; and a compensation value determining circuit configured to determine a read voltage level compensation value corresponding to a difference between the number of the first state values of the sample data written to the memory and the number of the first state values of the read data read from the memory.
摘要翻译：半导体存储系统包括：差分确定电路，被配置为确定写入存储器的采样数据的第一状态值的数量与从存储器读取的读取数据的第一状态值的数量之间的差; 以及补偿值确定电路，被配置为确定对应于写入存储器的采样数据的第一状态值的数量与从该存储器读取的读取数据的第一状态值的数量之间的差对应的读取电压电平补偿值记忆。

10. 发明授权

US08949687B2 Memory device and memory system 有权
标题翻译：内存设备和内存系统
公开(公告)号：US08949687B2
公开(公告)日：2015-02-03
申请号：US13396791
申请日：2012-02-15
申请人： Man-keun Seo , Jun-jin Kong , Kyoung-Lae Cho
发明人： Man-keun Seo , Jun-jin Kong , Kyoung-Lae Cho
IPC分类号： G11C29/00 , H03M7/30 , H03M13/05 , G06F11/10
CPC分类号： H03M13/2906 , G06F11/1012 , G06F11/1044 , H03M7/30 , H03M13/05 , H03M13/6312
摘要： A memory device and a memory system, the memory system including a data compressor for generating compressed data by compressing program data in a first unit, and an error correction block generator for dividing the compressed data in a second unit to obtain a plurality of pieces of normal data, and generating error correction blocks for correcting errors of the plurality of pieces of normal data, wherein each of the error correction blocks comprises the normal data, invalid data having a size corresponding to the size of the normal data, and parities for the normal data and the invalid data.
摘要翻译：存储器装置和存储器系统，所述存储器系统包括用于通过压缩第一单元中的程序数据产生压缩数据的数据压缩器，以及用于在第二单元中分割压缩数据的纠错块发生器，以获得多个正常数据和生成用于校正多条正常数据的错误的纠错块，其中每个纠错块包括正常数据，具有与正常数据的大小相对应的大小的无效数据，以及用于正常数据和无效数据。

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