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1. 发明授权

US06706615B2 Method of manufacturing a transistor 有权
标题翻译：制造晶体管的方法
公开(公告)号：US06706615B2
公开(公告)日：2004-03-16
申请号：US10401672
申请日：2003-03-31
申请人： Mizue Kitada , Toshiyuki Takemori , Shinji Kunori
发明人： Mizue Kitada , Toshiyuki Takemori , Shinji Kunori
IPC分类号： H01L2176
CPC分类号： H01L29/7813 , H01L29/04 , H01L29/0634 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/66348 , H01L29/7397
摘要： A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.
摘要翻译：提供了降低晶体管的导通电阻的技术。本发明的功率MOSFET具有半导体材料，该半导体材料设置在多晶硅栅极下方，并以低浓度杂质杂质的多晶硅构成。因此，耗尽层在多晶硅栅极下扩展到半导体材料的内部。由于电场强度从漏极层的表面到半导体材料的底面的深度均匀，并且在一个部位不产生高电场，所以晶体管的雪崩击穿电压增加。因此，可以使漏层中的杂质浓度高于常规晶体管中的杂质浓度，从而可以降低晶体管1的导通电阻。

2. 发明授权

US5262669A Semiconductor rectifier having high breakdown voltage and high speed operation 失效
标题翻译：具有高击穿电压和高速运行的半导体整流器
公开(公告)号：US5262669A
公开(公告)日：1993-11-16
申请号：US870268
申请日：1992-04-17
申请人： Masaru Wakatabe , Mitsugu Tanaka , Shinji Kunori
发明人： Masaru Wakatabe , Mitsugu Tanaka , Shinji Kunori
IPC分类号： H01L29/861 , H01L29/872 , H01L29/48
CPC分类号： H01L29/872 , H01L29/861 , Y10S257/916
摘要： A semiconductor rectifier having a high breakdown voltage and a high speed operation is provided, which includes a semiconductor substrate having an N.sup.+ -type semiconductor layer and an N-type semiconductor layer, a P.sup.+ -type semiconductor layer formed in the N-type semiconductor layer to provide a PN junction therebetween, the P.sup.+ -type semiconductor layer defining exposed regions of the N-type semiconductor layer, and a metal layer provided on an entire surface of the semiconductor substrate having the P.sup.+ -type semiconductor layer to provide contact surfaces of Schottky barrier between the metal layer and each of the exposed regions of the N-type semiconductor layer. In the structure, a configuration of the PN junction is provided to satisfy conditions given by 0.degree.
摘要翻译：提供具有高击穿电压和高速度操作的半导体整流器，其包括具有N +型半导体层和N型半导体层的半导体衬底，形成在N型半导体层中的P +型半导体层在其间提供PN结，P +型半导体层限定N型半导体层的暴露区域，以及设置在具有P +型半导体层的半导体衬底的整个表面上的金属层，以提供肖特基金属层与N型半导体层的每个暴露区域之间的阻挡层。在该结构中，提供PN结的配置以满足由0°θ= 135°和3Wbi

3. 发明申请

US20070194364A1 Diode 有权
标题翻译：二极管
公开(公告)号：US20070194364A1
公开(公告)日：2007-08-23
申请号：US11785808
申请日：2007-04-20
申请人： Mizue Kitada , Kosuke Oshima , Toru Kurosaki , Shinji Kunori , Akihiko Sugai
发明人： Mizue Kitada , Kosuke Oshima , Toru Kurosaki , Shinji Kunori , Akihiko Sugai
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0619 , H01L29/0634 , H01L29/66143 , H01L29/66348 , H01L29/7397 , H01L29/872
摘要： A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.
摘要翻译：提供具有低电阻和高击穿电压的晶体管和二极管。当具有长方体形状的窄沟槽的底部填充有通过外延方法生长的半导体时，{0.10}平面在窄沟槽的侧壁处露出。在窄沟槽的每个侧壁上以恒定速率外延生长半导体; 从而产生其中不存在空隙的填充材料。填充材料的浓度和宽度被优化。当填充材料完全耗尽时，这允许位于排水层中的填充材料之间的部分被完全耗尽; 从而能够在漏极层中延伸的耗尽层中建立具有恒定强度的电场。

4. 发明申请

US20060063335A1 Semiconductor device 有权
公开(公告)号：US20060063335A1
公开(公告)日：2006-03-23
申请号：US10967657
申请日：2004-10-19
申请人： Toru Kurosaki , Hiroaki Shishido , Mizue Kitada , Shinji Kunori , Kosuke Ohshima
发明人： Toru Kurosaki , Hiroaki Shishido , Mizue Kitada , Shinji Kunori , Kosuke Ohshima
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0692 , H01L29/0696 , H01L29/4238 , H01L29/66348 , H01L29/7397 , H01L29/7811 , H01L29/872
摘要： A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.

5. 发明授权

US07365391B2 Semiconductor device and method for manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07365391B2
公开(公告)日：2008-04-29
申请号：US11528637
申请日：2006-09-28
申请人： Toru Kurosaki , Shinji Kunori , Mizue Kitada , Kosuke Ohshima , Hiroaki Shishido , Masato Mikawa
发明人： Toru Kurosaki , Shinji Kunori , Mizue Kitada , Kosuke Ohshima , Hiroaki Shishido , Masato Mikawa
IPC分类号： H01L31/00
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.
摘要翻译：提供具有高耐压的半导体器件。活动槽22a包括长而窄的主槽部26和与主槽部的纵向侧面连接的副槽部27以及高度低于底面的第二导电型的埋入区域24 第二导电类型的基底扩散区域32a设置在主槽部分26的底表面上。在子槽部27中设置有与基底扩散区域32a相接触的第二导电类型的活动沟槽填充区域25。埋入区域24通过有源沟槽填充区域25与基极扩散区域32a接触。由于一个栅极沟槽83由一个有源槽22a中的掩埋区域24上方的部分形成，所以栅电极插塞48不分离，这允许电极图案被简化。

6. 发明授权

US07208375B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07208375B2
公开(公告)日：2007-04-24
申请号：US10967657
申请日：2004-10-19
申请人： Toru Kurosaki , Hiroaki Shishido , Mizue Kitada , Shinji Kunori , Kosuke Ohshima
发明人： Toru Kurosaki , Hiroaki Shishido , Mizue Kitada , Shinji Kunori , Kosuke Ohshima
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0692 , H01L29/0696 , H01L29/4238 , H01L29/66348 , H01L29/7397 , H01L29/7811 , H01L29/872
摘要： A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.
摘要翻译：提供了一种提高晶体管耐破坏性的技术。在本发明的晶体管中，填充区域的高度高于掩埋区域的高度，使得填充区域的耐受电压高于掩埋区域的耐受电压。因此，由于在有源区域发生雪崩击穿，导致雪崩击穿电流流过具有大面积的有源区域，不会发生电流集中。结果，增加了抵抗击穿的元件的坚固性。

7. 发明授权

US06876034B2 Semiconductor device having active grooves 有权
标题翻译：具有有源凹槽的半导体器件
公开(公告)号：US06876034B2
公开(公告)日：2005-04-05
申请号：US10607083
申请日：2003-06-27
申请人： Toru Kurosaki , Hiroaki Shishido , Mizue Kitada , Shinji Kunori , Kosuke Ohshima
发明人： Toru Kurosaki , Hiroaki Shishido , Mizue Kitada , Shinji Kunori , Kosuke Ohshima
IPC分类号： H01L21/331 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/47 , H01L29/739 , H01L29/78 , H01L29/872 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0692 , H01L29/0696 , H01L29/66348 , H01L29/7397 , H01L29/7811 , H01L29/872
摘要： A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.
摘要翻译：提供了具有均匀填充有半导体填料的槽的半导体器件。每个窄活动槽的两端连接到围绕有源槽的内周槽。有源沟槽两端的半导体填料的生长速度与其中心部分的生长速度相等。结果，获得了具有均匀高度填充有半导体填料的有源沟槽的半导体器件。

8. 发明授权

US06573559B2 Transistor and method of manufacturing the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US06573559B2
公开(公告)日：2003-06-03
申请号：US09793964
申请日：2001-02-28
申请人： Mizue Kitada , Toshiyuki Takemori , Shinji Kunori
发明人： Mizue Kitada , Toshiyuki Takemori , Shinji Kunori
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/04 , H01L29/0634 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/66348 , H01L29/7397
摘要： A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.
摘要翻译：提供了降低晶体管的导通电阻的技术。本发明的功率MOSFET具有半导体材料，该半导体材料设置在多晶硅栅极下方，并以低浓度杂质杂质的多晶硅构成。因此，耗尽层在多晶硅栅极下扩展到半导体材料的内部。由于电场强度从漏极层的表面到半导体材料的底面的深度均匀，并且在一个部位不产生高电场，所以晶体管的雪崩击穿电压增加。因此，可以使漏层中的杂质浓度高于常规晶体管中的杂质浓度，从而可以降低晶体管1的导通电阻。

9. 发明授权

US06404032B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06404032B1
公开(公告)日：2002-06-11
申请号：US09820837
申请日：2001-03-30
申请人： Mizue Kitada , Shinji Kunori
发明人： Mizue Kitada , Shinji Kunori
IPC分类号： H01L2947
CPC分类号： H01L29/66143 , H01L29/0634 , H01L29/872
摘要： Trenches are formed in the surface of a second semiconductor layer of a first conductivity type. A semiconductor filled material of a second conductivity type is filled in the trench. A Schottky metal electrode is formed on the surface of the second semiconductor layer and the surface of the semiconductor filled material. A Schottky junction is formed between the Schottky metal electrode and the second semiconductor layer. An ohmic contact is formed between the Schottky metal electrode and the semiconductor filled material. An avalanche breakdown voltage is increased when the impurity concentration of the second semiconductor layer and the semiconductor filled material and the interval between the trenches are set such that both the second semiconductor layer interposed between the semiconductor filled materials and the semiconductor filled material are completely depleted when the Schottky junction is reverse biased.
摘要翻译：沟槽形成在第一导电类型的第二半导体层的表面中。在沟槽中填充第二导电类型的半导体填充材料。在第二半导体层的表面和半导体填充材料的表面上形成肖特金属电极。在肖特基金属电极和第二半导体层之间形成肖特基结。在肖特基金属电极和半导体填充材料之间形成欧姆接触。当第二半导体层和半导体填充材料的杂质浓度和沟槽之间的间隔被设定为使得介于半导体填充材料和半导体填充材料之间的第二半导体层两者都完全耗尽时，雪崩击穿电压增加，肖特基结是反向偏置的。

10. 发明授权

US5345100A Semiconductor rectifier having high breakdown voltage and high speed operation 失效
标题翻译：具有高击穿电压和高速运行的半导体整流器
公开(公告)号：US5345100A
公开(公告)日：1994-09-06
申请号：US119561
申请日：1993-09-13
申请人： Takashi Kan , Masaru Wakatabe , Mitsugu Tanaka , Shinji Kunori , Akira Sugiyama
发明人： Takashi Kan , Masaru Wakatabe , Mitsugu Tanaka , Shinji Kunori , Akira Sugiyama
IPC分类号： H01L29/861 , H01L29/78 , H01L23/00
CPC分类号： H01L29/8613
摘要： A semiconductor rectifier having a high breakdown voltage and a high speed operation is provided, which comprises a semiconductor substrate including a first semiconductor layer of one conductivity type and a second semiconductor layer of one conductivity type provided on the first semiconductor layer, a third semiconductor layer of an opposite conductivity type having a depth D and formed in the second semiconductor layer to provide a pn junction therebetween, the third semiconductor layer defining a plurality of exposed regions of the second semiconductor layer, each of the plurality of exposed regions of the second semiconductor layer having a width W, a relation between the depth D and the width W being given by D.gtoreq.0.5W, and a metal electrode provided on the substrate surface.
摘要翻译：提供具有高击穿电压和高速度操作的半导体整流器，其包括：半导体衬底，包括一个导电类型的第一半导体层和设置在第一半导体层上的一种导电类型的第二半导体层;第三半导体层具有深度D并形成在第二半导体层中以在其间提供pn结的相反导电类型的第二半导体层，第三半导体层限定第二半导体层的多个暴露区域，第二半导体的多个暴露区域中的每一个具有宽度W，深度D和宽度W之间的关系由D> / = 0.5W给出的层以及设置在基板表面上的金属电极。

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