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1. 发明申请

US20050145892A1 Mask, semiconductor device manufacturing method, and semiconductor device 审中-公开
标题翻译：掩模，半导体器件制造方法和半导体器件
公开(公告)号：US20050145892A1
公开(公告)日：2005-07-07
申请号：US10506147
申请日：2003-03-13
申请人： Shinichiro Nohdo , Shigeru Moriya
发明人： Shinichiro Nohdo , Shigeru Moriya
IPC分类号： G03F1/20 , H01L29/76 , G03C5/00 , H01L31/113
CPC分类号： G03F1/20 , H01J2237/31794
摘要： A mask capable of improving superimposing accuracy of patterns drawn on a plurality of masks, a production method of a semiconductor device capable of improving a yield of semiconductor devices, and a semiconductor device wherein a pattern can be made finer are provided. A mask including a plurality of mask regions formed with mutually different mask patterns to be transferred to the same device, wherein all the mask patterns are drawn by the same electron beam exposure means; the mask pattern of each mask is drawn with being divided to a plurality of deflection regions; the deflection region is in a range wherein a part of the mask pattern can be drawn on the mask by deflecting an electron beam by fixing the electron beam exposure means; and the deflection region is divided, so that the mask pattern in any deflection region of each of the masks is transferred on the same region on the device as a mask pattern in one deflection region of other mask, a production method of a semiconductor device using the mask and a semiconductor device produced using the mask.
摘要翻译：提供能够提高在多个掩模上绘制的图案的叠加精度的掩模，提供能够提高半导体器件的产量的半导体器件的制造方法以及可以使图案更细的半导体器件。一种掩模，其包括形成有相互不同的掩模图案的多个掩模区域以转移到同一器件，其中所有掩模图案由相同的电子束曝光装置绘制; 每个掩模的掩模图案被划分成多个偏转区域; 偏转区域处于通过固定电子束曝光装置而使电子束偏转而能够在掩模上绘制一部分掩模图案的范围内; 并且偏转区域被分割，使得每个掩模的任何偏转区域中的掩模图案在与其他掩模的一个偏转区域中作为掩模图案的器件上的相同区域上转印，使用半导体器件的制造方法掩模和使用掩模制造的半导体器件。

2. 发明授权

US07456031B2 Exposure device, exposure method, and semiconductor device manufacturing method 失效
标题翻译：曝光装置，曝光方法和半导体器件制造方法
公开(公告)号：US07456031B2
公开(公告)日：2008-11-25
申请号：US10534917
申请日：2003-11-13
申请人： Shinji Omori , Shigeru Moriya , Shinichiro Nohdo
发明人： Shinji Omori , Shigeru Moriya , Shinichiro Nohdo
IPC分类号： H01L31/26 , H01L21/66
CPC分类号： B82Y40/00 , B82Y10/00 , G03F1/20 , H01J37/304 , H01J37/3174
摘要： To provide an exposure apparatus and an exposure method able to correct an image-placement error during an exposure which is unable to decrease only by correcting electron beam description data of a mask pattern, and a semiconductor device manufacturing method used the same, wherein an image placement R2 of a mask is measured at an inversion posture against an exposure posture (ST7), the measured image placement R2 is corrected with considering a pattern displacement caused by gravity at the exposure posture and a first correction data Δ1 is prepared based on a difference of the corrected image placement and a designed data (ST10), and an exposure is performed by deflecting charged particle beam to correct a position of a pattern to be exposed to a subject based on the first correction data Δ1 (ST13).
摘要翻译：为了提供一种曝光装置和曝光方法，能够通过校正掩膜图案的电子束描述数据而不能减小曝光期间的图像放置误差，以及使用其的半导体器件制造方法，其中图像以与曝光姿势相反的反转姿势（ST7）测量掩模的放置R 2，考虑由曝光姿势引起的重力引起的图案位移，并且准备第一校正数据Delta 1来校正测量图像布置R 2 基于校正图像放置的差异和设计数据（ST10），并且通过基于第一校正数据Delta 1来对带电粒子束进行偏转来校正要暴露于对象的图案的位置来执行曝光（ ST 13）。

3. 发明申请

US20070115471A1 WAFER, EXPOSURE MASK, METHOD OF DETECTING MARK AND METHOD OF EXPOSURE 审中-公开
标题翻译：防潮，曝光掩模，检测标记的方法和接触方法
公开(公告)号：US20070115471A1
公开(公告)日：2007-05-24
申请号：US11622534
申请日：2007-01-12
申请人： Shinichiro Nohdo
发明人： Shinichiro Nohdo
IPC分类号： G01B11/00
CPC分类号： G03F9/703 , G03F9/7038 , G03F9/7076 , G03F9/7088
摘要： A wafer, exposure mask, method for detecting an alignment mark and method for exposure, which make it possible to improve accuracy of the alignment as well as correction of a gap between the wafer and the exposure mask, are provided. There is provided a wafer having alignment marks (wafer marks) with edges for causing inspection light for alignment to scatter at an exposure surface during proximity exposure. The wafer mark is characterized by having dot pattern groups, which are made up of dot patterns arrayed in a predetermined direction. The dot pattern group is configured by arranging dot patterns in Direction X with an arrangement interval P2. The arrangement interval P2 is wider than an arrangement interval P1 for the dot patterns. Further, there is provided an exposure mask, which is used in similar proximity exposure, having alignment marks, as mask marks, which have a similar configuration as that of the wafer marks.
摘要翻译：提供了晶片，曝光掩模，用于检测对准标记的方法和用于曝光的方法，这使得可以提高对准精度以及校正晶片和曝光掩模之间的间隙。提供了具有边缘的对准标记（晶片标记）的晶片，用于使得检测光对准以在接近曝光期间在曝光表面处散射。晶片标记的特征在于具有点阵图案组，其由沿预定方向排列的点图案组成。点阵图案组通过以方向X排列点阵图形配置，排列间隔P 2。布置间隔P 2比点图案的布置间隔P 1宽。此外，提供了具有类似接近曝光的曝光掩模，具有与晶片标记类似的配置的对准标记作为掩模标记。

4. 发明申请

US20060152723A1 Complementary division mask having alignment mark, method for forming alignment mark of the complementary division mask, semiconductor device manufactured by using the complementary division mask, and its manufacturing method 审中-公开
标题翻译：具有对准标记的互补分割掩模，用于形成互补分割掩模的对准标记的方法，使用互补分割掩模制造的半导体器件及其制造方法
公开(公告)号：US20060152723A1
公开(公告)日：2006-07-13
申请号：US10523563
申请日：2003-08-05
申请人： Shinichiro Nohdo , Keiko Amai
发明人： Shinichiro Nohdo , Keiko Amai
IPC分类号： G01B11/00
CPC分类号： G03F1/20 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01J2237/30438
摘要： In fabrication of a semiconductor device having plural patterns on a plurality of layers by using complementary divided masks each having alignment marks distributed therein, because of the presence of a plurality of complementary divided mask layers, misalignment between respective layers tends to occur. To solve this problem, divided alignment marks (M1a, M2a, M3a, M4a) are formed in respective complementary divided regions corresponding to respective blocks (B1, B2, B3, B4) of complementary divided masks obtained by dividing a stencil mask. By distributing alignment marks to respective complementary divided masks, a positional deviation between respective masks is averaged, thereby enabling to fabricate a semiconductor device in which a large positional deviation between patterns of adjoining layers is eliminated.
摘要翻译：在通过使用分布在其中的对准标记的互补分割掩模在多层上制造具有多个图案的半导体器件时，由于存在多个互补分割掩模层，所以各层之间的偏移趋于发生。为了解决这个问题，分别的对准标记（M 1 a，M 2 a，M 3 a，M 4 a）形成在与各个块（B 1，B 2，B 3，B 4）对应的各个互补分割区域通过分割模板掩模获得的互补分割掩模。通过将对准标记分配到相应的互补分割掩模，对各个掩模之间的位置偏差进行平均化，从而能够制造其中相邻层的图案之间的大的位置偏移消除的半导体器件。

5. 发明申请

US20060151710A1 Exposure device, exposure method, and semiconductor device manufacturing method 失效
标题翻译：曝光装置，曝光方法和半导体器件制造方法
公开(公告)号：US20060151710A1
公开(公告)日：2006-07-13
申请号：US10534917
申请日：2003-11-13
申请人： Shinji Omori , Shigeru Moriya , Shinichiro Nohdo
发明人： Shinji Omori , Shigeru Moriya , Shinichiro Nohdo
IPC分类号： H01J3/14 , A61N5/00
CPC分类号： B82Y40/00 , B82Y10/00 , G03F1/20 , H01J37/304 , H01J37/3174
摘要： To provide an exposure apparatus and an exposure method able to correct an image-placement error during an exposure which is unable to decrease only by correcting electron beam description data of a mask pattern, and a semiconductor device manufacturing method used the same, wherein an image placement R2 of a mask is measured at an inversion posture against an exposure posture (ST7), the measured image placement R2 is corrected with considering a pattern displacement caused by gravity at the exposure posture and a first correction data Δ1 is prepared based on a difference of the corrected image placement and a designed data (ST10), and an exposure is performed by deflecting charged particle beam to correct a position of a pattern to be exposed to a subject based on the first correction data Δ1 (ST13).
摘要翻译：为了提供一种曝光装置和曝光方法，能够通过校正掩膜图案的电子束描述数据而不能减小曝光期间的图像放置误差，以及使用其的半导体器件制造方法，其中图像以与曝光姿势相反的反转姿势（ST7）测量掩模的放置R 2，考虑由曝光姿势引起的重力引起的图案位移，并且准备第一校正数据Delta 1来校正测量图像布置R 2 基于校正图像放置的差异和设计数据（ST10），并且通过基于第一校正数据Delta 1来对带电粒子束进行偏转来校正要暴露于对象的图案的位置来执行曝光（ ST 13）。

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