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1. 发明授权

US07955956B2 Method for recycling/reclaiming a monitor wafer 有权
标题翻译：回收/回收监控晶圆的方法
公开(公告)号：US07955956B2
公开(公告)日：2011-06-07
申请号：US12621393
申请日：2009-11-18
申请人： Gary C. Barrett , Bradley D. Bucher , Colin L. Carr
发明人： Gary C. Barrett , Bradley D. Bucher , Colin L. Carr
IPC分类号： H01L21/322 , H01L21/00 , H01L31/26 , H01L21/66
CPC分类号： H01L21/02079 , H01L21/02032 , H01L21/3225 , H01L22/34
摘要： The invention provides a method for recycling/reclaiming a monitor or test wafer and a method for testing an integrated circuit manufacturing process. After a monitor wafer has been used for testing one or more semiconductor wafer processing steps to determine adequacy for use with production wafers, deposited materials and other residues from the tested processing steps are removed, and the stripped wafer is subjected to a thermal anneal to repair defects in its surface and return it to a reusable condition.
摘要翻译：本发明提供一种用于回收/回收监视器或测试晶片的方法以及用于测试集成电路制造过程的方法。在监测晶片已被用于测试一个或多个半导体晶片处理步骤以确定用于生产晶片的充分性之后，从被测试的处理步骤中去除沉积材料和其它残留物，并且剥离的晶片经受热退火以修复其表面缺陷并使其恢复到可重复使用的状态。

2. 发明授权

US07598100B2 Manufacturing method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07598100B2
公开(公告)日：2009-10-06
申请号：US11719112
申请日：2004-11-18
申请人： Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Masayoshi Okamoto , Yasunori Narizuka
发明人： Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Yasuhiro Motoyama , Masayoshi Okamoto , Yasunori Narizuka
IPC分类号： H01L21/00 , H01L31/26 , H01L21/66 , H01L21/82
CPC分类号： G01R1/0735 , G01R3/00
摘要： As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.
摘要翻译：随着用于防止多层布线基板1翘曲的卡夹的厚度增加，存在薄膜片2被埋在卡夹中并且不能实现探针7和测试垫之间的牢固接触的问题。为了防止，薄膜片2和接合环6在仅向薄膜片2的中心区域IA施加张力的状态下接合，并且拉伸力不施加到外围区域 OA。然后，限定高达薄膜片2的探针表面的高度的接合环6的高度增加，从而增加高达薄膜片2的探针表面的高度。

3. 发明授权

US07294516B2 Test patterns and methods of controlling CMP process using the same 失效
标题翻译：使用该方法控制CMP工艺的测试模式和方法
公开(公告)号：US07294516B2
公开(公告)日：2007-11-13
申请号：US11055505
申请日：2005-02-10
申请人： Jeong-Heon Park , Bo-Un Yoon , Jae-Dong Lee
发明人： Jeong-Heon Park , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L31/26 , H01L23/58
CPC分类号： H01L22/32 , H01L22/34
摘要： A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.
摘要翻译：提供了一种测试图案和使用其的CMP控制方法。测试图案设置在具有主区域和监视区域的半导体衬底的监视区域上。测试图案包括平面区域和图案区域。该方法包括设置测试图案的阶梯差和主图案的蚀刻厚度之间的相关性，然后将CMP施加到具有测试图案和主图案的半导体衬底预定时间。测量测试图案的阶差，并根据相关性确定对应于测试图案的阶差的主图案的蚀刻厚度。通过将确定的主图案的蚀刻厚度与参考值进行比较来校正抛光时间，并且将修正的抛光时间应用于随后的批次或随后的基板。

4. 发明授权

US07179664B2 Method for generating work-in-process schedules 有权
标题翻译：生成在制程序时间表的方法
公开(公告)号：US07179664B2
公开(公告)日：2007-02-20
申请号：US10840099
申请日：2004-05-06
申请人： Shu Chen Huang , Gwo-Chiang Fang
发明人： Shu Chen Huang , Gwo-Chiang Fang
IPC分类号： H01L31/26
CPC分类号： G05B19/41865 , G05B2219/45031 , H01L22/20 , Y02P90/20
摘要： A method and program is disclosed for generating work in progress (WIP) schedules in semiconductor manufacturing facility. After determining starting and ending dates of predetermined schedule periods for generating WIP schedules, remaining days are determined for completing at least one wafer lot associated with predetermined product from the starting date. A starting process stage for the wafer lot is determined at the starting date based on the remaining days, and an ending process stage for the wafer lot at the end of the ending date. Wafer numbers are assigned to each process stage of schedule times in proportion to process times of each stage in view of total process time for the schedule period, and by repeating the above steps for one or more other wafer lots under production, a total wafer number assigned to each stage is determined and the WIP schedule for the schedule period is obtained.
摘要翻译：公开了用于在半导体制造设备中生成正在进行的工作（WIP）计划的方法和程序。在确定用于产生WIP时间表的预定调度周期的开始和结束日期之后，确定剩余天数以从起始日期完成与预定产品相关联的至少一个晶片批次。基于剩余天数的开始日期确定晶圆批次的起始处理阶段，以及在结束日期结束时的晶圆批次的结束处理阶段。考虑到进度周期的总处理时间，并且通过对生产中的一个或多个其他晶片批次重复上述步骤，将晶片号码分配给每个阶段的每个处理阶段与每个阶段的处理时间成比例，总晶片数确定分配给每个阶段的时间段的WIP时间表。

5. 发明授权

US07074628B2 Test structure and method for yield improvement of double poly bipolar device 失效
公开(公告)号：US07074628B2
公开(公告)日：2006-07-11
申请号：US10947069
申请日：2004-09-22
申请人： Bradley J. Albers , Thomas Craig Esry , Daniel Charles Kerr , Edward Paul Martin, Jr. , Oliver Desmond Patterson
发明人： Bradley J. Albers , Thomas Craig Esry , Daniel Charles Kerr , Edward Paul Martin, Jr. , Oliver Desmond Patterson
IPC分类号： H01L31/26 , H01L21/66
CPC分类号： H01L22/34 , G01R31/2648 , G01R31/2884 , G01R31/307
摘要： A method and apparatus for identifying crystal defects in emitter-base junctions of NPN bipolar transistors uses a test structure having an NP junction that can be inspected using passive voltage contrast. The test structure eliminates the collector of the transistor and simulates only the emitter and base. Eliminating the collector removes an NP junction between collector and substrate of a wafer allowing charge to flow from the substrate to emitter if the emitter-base junction is defective since only one NP junction exists in the test structure. In one embodiment, the test structures are located between dies on a wafer and may be formed in groups of several thousand.

6. 发明授权

US08310068B2 TCP-type semiconductor device 失效
标题翻译： TCP型半导体器件
公开(公告)号：US08310068B2
公开(公告)日：2012-11-13
申请号：US12805017
申请日：2010-07-07
申请人： Suguru Sasaki
发明人： Suguru Sasaki
IPC分类号： H01L23/08 , H01L23/48 , H01L31/26
CPC分类号： H01L23/4985 , H01L2924/0002 , H01L2924/00
摘要： A TCP type semiconductor device, which is connected to a plurality of substrate-side electrodes parallel to each other and each having a linear shape, has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film and electrically connecting between the semiconductor chip and the plurality of substrate-side electrodes, respectively. Each of the plurality of leads has an external terminal section extending in a first direction and configured to come in contact with corresponding one of the plurality of substrate-side electrodes. A part of the external terminal section is a wide section that is formed wider than the other section of the external terminal section A position of the wide section in the first direction is different between adjacent leads of the plurality of leads.
摘要翻译：连接到彼此平行并且各自具有直线形状的多个基板侧电极的TCP型半导体器件具有：基膜; 安装在基膜上的半导体芯片; 以及形成在所述基膜上并分别电连接所述半导体芯片和所述多个基板侧电极的多个引线。所述多个引线中的每一个具有沿第一方向延伸的外部端子部，并且被配置为与所述多个基板侧电极中的相应一个电极接触。外部端子部分的一部分是形成为比外部端子部分A的另一部分宽的宽部分。在多个引线的相邻引线之间，第一方向上的宽部分的位置不同。

7. 发明授权

US07422913B2 Method for checking a condition of a heat treatment 失效
标题翻译：检查热处理条件的方法
公开(公告)号：US07422913B2
公开(公告)日：2008-09-09
申请号：US10852007
申请日：2004-05-24
申请人： Min-Rei Jiang
发明人： Min-Rei Jiang
IPC分类号： H01L31/26 , H01L21/66
CPC分类号： G01K11/12 , H01R12/7076 , H01R43/0242 , H05K1/0269 , H05K3/3494 , H05K2203/161 , H05K2203/163
摘要： A method for connecting terminals is provided. The method includes steps of a) providing a board having a first terminal thereon; b) performing a check of a heat treatment by using a thermal sensitive paper in order to determine a optimal condition of the heat treatment for the board; c) heating the first terminal under the optimal condition of the heat treatment; and d) connecting a second terminal to the heated first terminal.
摘要翻译：提供了一种用于连接端子的方法。该方法包括以下步骤：a）提供其上具有第一端子的板; b）通过使用热敏纸进行热处理检查，以确定板的热处理的最佳状态; c）在热处理的最佳条件下加热第一端子; 以及d）将第二端子连接到被加热的第一端子。

8. 发明授权

US07186575B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07186575B2
公开(公告)日：2007-03-06
申请号：US11064500
申请日：2005-02-23
申请人： Daisuke Ito , Toshimi Kawahara
发明人： Daisuke Ito , Toshimi Kawahara
IPC分类号： H01L31/26 , H01L21/66
CPC分类号： H01L22/22 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05147 , H01L2224/05155 , H01L2224/05171 , H01L2224/05568 , H01L2224/05644 , H01L2224/11 , H01L2924/00014
摘要： In a method for manufacturing a semiconductor device by processing of a wafer level, in the case of forming the semiconductor device at the wafer level, on the basis of inspection results on individual semiconductor chips constituting a semiconductor wafer, a treatment for forming a circuit including a rewiring pattern is performed with respect to a semiconductor chip judged as a conforming product and a treatment in which a rewiring pattern is not formed in order to avoid having adverse influence on a semiconductor device of a conforming product or an inspection apparatus in an inspection of a formed semiconductor device after forming the semiconductor device is performed with respect to a semiconductor chip judged as a nonconforming product.
摘要翻译：在通过晶片级的处理制造半导体器件的方法中，在基于晶片级形成半导体器件的情况下，基于构成半导体晶片的各个半导体芯片的检查结果，形成电路的处理包括对于被判定为符合产品的半导体芯片和未形成重新布线图案的处理来执行重新布线图案，以避免对符合产品的半导体器件或检查装置的检查产生不利影响相对于被判定为不合格品的半导体芯片进行形成半导体器件后的形成的半导体器件。

9. 发明授权

US07098050B1 Corona based charge voltage measurement 有权
标题翻译：基于电晕的充电电压测量
公开(公告)号：US07098050B1
公开(公告)日：2006-08-29
申请号：US10974270
申请日：2004-10-27
申请人： Sergio Edelstein , Eric F. Bouche , Jianou Shi , Shiyou Pei , Xiafang Zhang
发明人： Sergio Edelstein , Eric F. Bouche , Jianou Shi , Shiyou Pei , Xiafang Zhang
IPC分类号： H01L31/26
CPC分类号： G01R31/303 , G01R31/2648 , H01L22/14
摘要： A method of measuring electrical characteristics of a gate dielectric. The gate dielectric is local annealed by directing a highly localized energy source at the measurement area, such that the measurement area is brought to an annealing temperature while surrounding structures are not significantly heated. While heating the measurement area, a flow of a gas containing a percentage of hydrogen, deuterium, or water vapor at a flow rate is directed to the measurement area. A charge is inducted on the measurement area and the electrical characteristics of the gate dielectric are measured using non contact electrical probing.
摘要翻译：测量栅极电介质的电特性的方法。栅极电介质通过在测量区域处引导高度局部化的能量源进行局部退火，使得测量区域达到退火温度，而周围结构不被显着加热。在加热测量区域的同时，以一定的流量将含有一定百分比的氢，氘或水蒸汽的气体流动到测量区域。在测量区域上引入电荷，并且使用非接触电探测来测量栅极电介质的电特性。

10. 发明授权

US07033845B2 Phase control of megasonic RF generator for optimum operation 有权
标题翻译：超声波发生器的相位控制，以实现最佳运行
公开(公告)号：US07033845B2
公开(公告)日：2006-04-25
申请号：US10360320
申请日：2003-02-06
申请人： Thomas W. Anderson , Robert Knop
发明人： Thomas W. Anderson , Robert Knop
IPC分类号： H01L31/26 , H01L21/66 , B08B6/00 , B08B3/12 , C25F5/00
CPC分类号： H01L21/67253 , B06B1/0253 , B06B2201/71 , B08B3/12 , H01L21/67057 , Y10S134/902
摘要： A system and method of providing RF to a transducer includes an oscillator, an RF generator, and a voltage phase detector. The oscillator has a frequency control input and an RF signal output. The RF generator has an input coupled to the oscillator RF signal output and an RF generator output coupled to the transducer. The voltage phase detector includes a first phase input coupled to the RF signal output of the oscillator, a second phase input coupled to the RF generator output, and a frequency control signal output coupled to the oscillator frequency control voltage input.
摘要翻译：向换能器提供RF的系统和方法包括振荡器，RF发生器和电压相位检测器。振荡器具有频率控制输入和RF信号输出。 RF发生器具有耦合到振荡器RF信号输出的输入端和耦合到换能器的RF发生器输出。电压相位检测器包括耦合到振荡器的RF信号输出的第一相位输入，耦合到RF发生器输出的第二相输入和耦合到振荡器频率控制电压输入的频率控制信号输出。

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