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1. 发明授权

US07879727B2 Method of fabricating a semiconductor device including a pattern of line segments 有权
标题翻译：制造包括线段图案的半导体器件的方法
公开(公告)号：US07879727B2
公开(公告)日：2011-02-01
申请号：US12354480
申请日：2009-01-15
申请人： Sergei Postnikov , Thomas Schulz , Hans-Joachim Barth , Klaus von Arnim
发明人： Sergei Postnikov , Thomas Schulz , Hans-Joachim Barth , Klaus von Arnim
IPC分类号： H01L21/311
CPC分类号： H01L27/11 , G03F7/40 , G03F7/7035 , H01L21/32139
摘要： A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.
摘要翻译：一种制造半导体器件的方法，包括在半导体器件的层上沉积硬掩模层，选择性地蚀刻硬掩模层中的连续线的图案，在硬掩模层的剩余部分上沉积抗反射涂层，将光致抗蚀剂层沉积在抗反射涂层，通过光刻工艺用多个隔离沟槽图案化光致抗蚀剂层，每个隔离沟槽垂直于并交叉下层硬掩模层的至少一条连续线的部分延伸，并且每个隔离沟槽具有初始宽度。该方法还包括通过收缩过程将每个隔离沟槽的宽度从初始宽度减小到期望宽度，蚀刻隔离沟槽下方的抗反射涂层以暴露下面的连续线的相交部分，并蚀刻暴露的相交部分硬掩模层的下面的连续线以形成具有以期望宽度分隔的线端部的线段的图案。

2. 发明申请

US20090209097A1 METHOD OF FORMING INTERCONNECTS 审中-公开
标题翻译：形成互连的方法
公开(公告)号：US20090209097A1
公开(公告)日：2009-08-20
申请号：US12032295
申请日：2008-02-15
申请人： Thomas Schulz , Sergei Postnikov , Hans-Joachim Barth , Klaus von Arnim
发明人： Thomas Schulz , Sergei Postnikov , Hans-Joachim Barth , Klaus von Arnim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0273 , H01L21/0338 , H01L21/31144
摘要： A method of forming interconnects includes etching a first set of openings in a hard mask using a first photo resist layer with a first pattern of openings as a first etch mask, and etching a second set of openings in the hard mask using a second photo resist layer with a second pattern of openings as a second etch mask. The method includes shrinking the openings in at least one of the first pattern and the second pattern prior to etching the openings in the hard mask.
摘要翻译：一种形成互连的方法包括使用具有第一开口图案的第一光致抗蚀剂层作为第一蚀刻掩模蚀刻在硬掩模中的第一组开口，以及使用第二光致抗蚀剂蚀刻硬掩模中的第二组开口层，其具有作为第二蚀刻掩模的第二开口图案。该方法包括在蚀刻硬掩模中的开口之前收缩第一图案和第二图案中的至少一个中的开口。

3. 发明授权

US08698206B2 Feature patterning methods and structures thereof 有权
标题翻译：特征图案化方法及其结构
公开(公告)号：US08698206B2
公开(公告)日：2014-04-15
申请号：US13096802
申请日：2011-04-28
申请人： Thomas Schulz , Sergei Postnikov
发明人： Thomas Schulz , Sergei Postnikov
IPC分类号： H01L27/10
CPC分类号： H01L23/52 , H01L21/027 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.
摘要翻译：公开了图形特征的方法，制造半导体器件的方法和半导体器件。在一个实施例中，图案化特征的方法包括在第一材料层中形成特征的第一部分。特征的第二部分形成在第一材料层中，并且特征的第三部分形成在第二材料层中。

4. 发明授权

US07981789B2 Feature patterning methods and structures thereof 有权
标题翻译：特征图案化方法及其结构
公开(公告)号：US07981789B2
公开(公告)日：2011-07-19
申请号：US12271606
申请日：2008-11-14
申请人： Thomas Schulz , Sergei Postnikov
发明人： Thomas Schulz , Sergei Postnikov
IPC分类号： H01L21/4763
CPC分类号： H01L23/52 , H01L21/027 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.
摘要翻译：公开了图形特征的方法，制造半导体器件的方法和半导体器件。在一个实施例中，图案化特征的方法包括在第一材料层中形成特征的第一部分。特征的第二部分形成在第一材料层中，并且特征的第三部分形成在第二材料层中。

5. 发明申请

US20100176479A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100176479A1
公开(公告)日：2010-07-15
申请号：US12354480
申请日：2009-01-15
申请人： Sergei Postnikov , Thomas Schulz , Hans-Joachim Barth , Klaus von Arnim
发明人： Sergei Postnikov , Thomas Schulz , Hans-Joachim Barth , Klaus von Arnim
IPC分类号： H01L29/68 , H01L21/762
CPC分类号： H01L27/11 , G03F7/40 , G03F7/7035 , H01L21/32139
摘要： A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.
摘要翻译：一种制造半导体器件的方法，包括在半导体器件的层上沉积硬掩模层，选择性地蚀刻硬掩模层中的连续线的图案，在硬掩模层的剩余部分上沉积抗反射涂层，将光致抗蚀剂层沉积在抗反射涂层，通过光刻工艺用多个隔离沟槽图案化光致抗蚀剂层，每个隔离沟槽垂直于并交叉下层硬掩模层的至少一条连续线的部分延伸，并且每个隔离沟槽具有初始宽度。该方法还包括通过收缩过程将每个隔离沟槽的宽度从初始宽度减小到期望宽度，蚀刻隔离沟槽下方的抗反射涂层以暴露下面的连续线的相交部分，并蚀刻暴露的相交部分硬掩模层的下面的连续线以形成具有以期望宽度分隔的线端部的线段的图案。

6. 发明申请

US20110215479A1 Feature Patterning Methods and Structures Thereof 有权
标题翻译：特征图案化方法及结构
公开(公告)号：US20110215479A1
公开(公告)日：2011-09-08
申请号：US13096802
申请日：2011-04-28
申请人： Thomas Schulz , Sergei Postnikov
发明人： Thomas Schulz , Sergei Postnikov
IPC分类号： H01L23/48
CPC分类号： H01L23/52 , H01L21/027 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.
摘要翻译：公开了图形特征的方法，制造半导体器件的方法和半导体器件。在一个实施例中，图案化特征的方法包括在第一材料层中形成特征的第一部分。特征的第二部分形成在第一材料层中，并且特征的第三部分形成在第二材料层中。

7. 发明授权

US07935547B2 Method of patterning a layer using a pellicle 有权
标题翻译：使用防护薄膜图案化层的方法
公开(公告)号：US07935547B2
公开(公告)日：2011-05-03
申请号：US12279672
申请日：2006-02-17
申请人： Kevin Lucas , Kyle Patterson , Sergei Postnikov
发明人： Kevin Lucas , Kyle Patterson , Sergei Postnikov
IPC分类号： H01L21/00
CPC分类号： G03F1/62 , G03F1/36
摘要： A method for patterning a layer on a semiconductor substrate includes forming a layer of a semiconductor substrate and exposing the layer to light. The light travels through a second pellicle that is manufactured by a method that includes determining a first transmission of a first light through a first pellicle, wherein the first light is normal to the first pellicle, determining a second transmission of a second light through the first pellicle, wherein the second light is not normal to the first pellicle, and modifying the first pellicle to form a second pellicle using the first and second transmission.
摘要翻译：用于在半导体衬底上图案化层的方法包括形成半导体衬底的层并将该层暴露于光。光穿过通过包括确定通过第一防护薄膜的第一光的第一透射的方法制造的第二防护薄膜，其中第一光垂直于第一防护薄膜，确定通过第一防护膜的第二光的第二透射防护薄膜，其中所述第二光不与所述第一防护薄膜正交，并且使用所述第一和第二透射来修饰所述第一防护薄膜以形成第二防护薄膜。

8. 发明申请

US20090130865A1 METHOD OF PATTERNING A LAYER USING A PELLICLE 有权
标题翻译：使用细胞膜分层的方法
公开(公告)号：US20090130865A1
公开(公告)日：2009-05-21
申请号：US12279672
申请日：2006-02-17
申请人： Kevin Lucas , Kyle Patterson , Sergei Postnikov
发明人： Kevin Lucas , Kyle Patterson , Sergei Postnikov
IPC分类号： H01L21/428
CPC分类号： G03F1/62 , G03F1/36
摘要： A method for patterning a layer on a semiconductor substrate includes forming a layer of a semiconductor substrate and exposing the layer to light. The light travels through a second pellicle that is manufactured by a method that includes determining a first transmission of a first light through a first pellicle, wherein the first light is normal to the first pellicle, determining a second transmission of a second light through the first pellicle, wherein the second light is not normal to the first pellicle, and modifying the first pellicle to form a second pellicle using the first and second transmission.
摘要翻译：用于在半导体衬底上图案化层的方法包括形成半导体衬底的层并将该层暴露于光。光穿过通过包括确定通过第一防护薄膜的第一光的第一透射的方法制造的第二防护薄膜，其中第一光垂直于第一防护薄膜，确定通过第一防护膜的第二光的第二透射防护薄膜，其中所述第二光不与所述第一防护薄膜正交，并且使用所述第一和第二透射来修饰所述第一防护薄膜以形成第二防护薄膜。

9. 发明申请

US20100123250A1 Feature Patterning Methods and Structures Thereof 有权
标题翻译：特征图案化方法及结构
公开(公告)号：US20100123250A1
公开(公告)日：2010-05-20
申请号：US12271606
申请日：2008-11-14
申请人： Thomas Schulz , Sergei Postnikov
发明人： Thomas Schulz , Sergei Postnikov
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L23/52 , H01L21/027 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.
摘要翻译：公开了图形特征的方法，制造半导体器件的方法和半导体器件。在一个实施例中，图案化特征的方法包括在第一材料层中形成特征的第一部分。特征的第二部分形成在第一材料层中，并且特征的第三部分形成在第二材料层中。

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