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1. 发明申请

US20080067697A1 INTEGRATED CIRCUIT WIRE PATTERNS INCLUDING INTEGRAL PLUG PORTIONS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：集成电路图案，包括整体插拔方式及其制作方法
公开(公告)号：US20080067697A1
公开(公告)日：2008-03-20
申请号：US11675829
申请日：2007-02-16
申请人： Seong-Goo Kim , Yung-Gi Kim , Jae-Man Yoon , Hyeoung-Won Seo
发明人： Seong-Goo Kim , Yung-Gi Kim , Jae-Man Yoon , Hyeoung-Won Seo
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L29/4236 , H01L21/28123 , H01L21/76834 , H01L21/76883 , H01L21/76897 , H01L23/52 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization. A surface of the plug portion may protrude to a substantially same level as a surface of the substrate adjacent to and outside the trench, and the surface of the recessed portion may be below the surface of the substrate outside the trench. Related fabrication methods are also discussed.
摘要翻译：集成电路器件包括其中包括沟槽的衬底和沟槽中的导电插头线图案。导电插头线图案包括露出沟槽的相对侧壁的部分的凹陷部分和从凹陷部分的表面突出的整体插塞部分，以提供与不同层级上的至少一个其它导电线图案的电连接的金属化。插塞部分的表面可以突出到与沟槽相邻并且在沟槽外部的衬底的表面基本相同的水平面，并且凹部的表面可以在沟槽外部的衬底的表面下方。还讨论了相关的制造方法。

2. 发明申请

US20100283094A1 SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US20100283094A1
公开(公告)日：2010-11-11
申请号：US12840599
申请日：2010-07-21
申请人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
发明人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.
摘要翻译：提供了具有垂直晶体管的半导体器件及其制造方法。该方法包括制备具有单元区域和外围电路区域的半导体衬底。在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。位线分离沟槽与垂直栅极结构的列方向平行地形成。位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

3. 发明授权

US07781285B2 Semiconductor device having vertical transistor and method of fabricating the same 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US07781285B2
公开(公告)日：2010-08-24
申请号：US11450936
申请日：2006-06-09
申请人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
发明人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
IPC分类号： H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.
摘要翻译：提供了具有垂直晶体管的半导体器件及其制造方法。该方法包括制备具有单元区域和外围电路区域的半导体衬底。在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。位线分离沟槽与垂直栅极结构的列方向平行地形成。位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

4. 发明授权

US07659597B2 Integrated circuit wire patterns including integral plug portions 有权
标题翻译：集成电路线图案，包括整体插头部分
公开(公告)号：US07659597B2
公开(公告)日：2010-02-09
申请号：US11675829
申请日：2007-02-16
申请人： Seong-Goo Kim , Yun-Gi Kim , Jae-Man Yoon , Hyeoung-Won Seo
发明人： Seong-Goo Kim , Yun-Gi Kim , Jae-Man Yoon , Hyeoung-Won Seo
IPC分类号： H01L23/52 , H01L21/336
CPC分类号： H01L29/4236 , H01L21/28123 , H01L21/76834 , H01L21/76883 , H01L21/76897 , H01L23/52 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization. A surface of the plug portion may protrude to a substantially same level as a surface of the substrate adjacent to and outside the trench, and the surface of the recessed portion may be below the surface of the substrate outside the trench. Related fabrication methods are also discussed.
摘要翻译：集成电路器件包括其中包括沟槽的衬底和沟槽中的导电插头线图案。导电插头线图案包括露出沟槽的相对侧壁的部分的凹陷部分和从凹陷部分的表面突出的整体插塞部分，以提供与不同层级上的至少一个其它导电线图案的电连接的金属化。插塞部分的表面可以突出到与沟槽相邻并且在沟槽外部的衬底的表面基本相同的水平面，并且凹部的表面可以在沟槽外部的衬底的表面下方。还讨论了相关的制造方法。

5. 发明申请

US20070080385A1 Semiconductor device having vertical transistor and method of fabricating the same 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US20070080385A1
公开(公告)日：2007-04-12
申请号：US11450936
申请日：2006-06-09
申请人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
发明人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
IPC分类号： H01L29/94
CPC分类号： H01L27/10894 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.
摘要翻译：提供了具有垂直晶体管的半导体器件及其制造方法。该方法包括制备具有单元区域和外围电路区域的半导体衬底。在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。位线分离沟槽与垂直栅极结构的列方向平行地形成。位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

6. 发明授权

US08174065B2 Semiconductor device having vertical transistor and method of fabricating the same 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US08174065B2
公开(公告)日：2012-05-08
申请号：US12840599
申请日：2010-07-21
申请人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
发明人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
IPC分类号： H01L29/66
CPC分类号： H01L27/10894 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.
摘要翻译：提供了具有垂直晶体管的半导体器件及其制造方法。该方法包括制备具有单元区域和外围电路区域的半导体衬底。在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。位线分离沟槽与垂直栅极结构的列方向平行地形成。位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

7. 发明授权

US08164119B2 Semiconductor device including conductive lines with fine line width and method of fabricating the same 有权
标题翻译：包括具有细线宽度的导线的半导体器件及其制造方法
公开(公告)号：US08164119B2
公开(公告)日：2012-04-24
申请号：US13014952
申请日：2011-01-27
申请人： Hyeoung-Won Seo , Byung-Hyug Roh , Seong-Goo Kim , Sang-Min Jeon
发明人： Hyeoung-Won Seo , Byung-Hyug Roh , Seong-Goo Kim , Sang-Min Jeon
IPC分类号： H01L27/10
CPC分类号： H01L27/10897 , H01L21/743 , H01L27/105 , H01L27/10882
摘要： A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.
摘要翻译：半导体器件包括半导体衬底，该半导体衬底包括第一芯区域和第二芯区域，第一芯区域和第二芯区域之间插入有单元阵列区域，第一导电线路和延伸到跨越单元阵列区域的第一芯区域的第二导电线，导电线和延伸到跨越单元阵列区域的第二芯区的第四导线，其中第一至第四导线的线宽小于光刻工艺中的分辨率极限。

8. 发明申请

US20110147800A1 SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LINES WITH FINE LINE WIDTH AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有精细线宽度的导电线的半导体器件及其制造方法
公开(公告)号：US20110147800A1
公开(公告)日：2011-06-23
申请号：US13014952
申请日：2011-01-27
申请人： Hyeoung-Won SEO , Byung-Hyug ROH , Seong-Goo Kim , Sang-Min Jeon
发明人： Hyeoung-Won SEO , Byung-Hyug ROH , Seong-Goo Kim , Sang-Min Jeon
IPC分类号： H01L27/10
CPC分类号： H01L27/10897 , H01L21/743 , H01L27/105 , H01L27/10882
摘要： A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.
摘要翻译：半导体器件包括半导体衬底，该半导体衬底包括第一芯区域和第二芯区域，第一芯区域和第二芯区域之间插入有单元阵列区域，第一导电线路和延伸到跨越单元阵列区域的第一芯区域的第二导电线，导电线和延伸到跨越单元阵列区域的第二芯区的第四导线，其中第一至第四导线的线宽小于光刻工艺中的分辨率极限。

9. 发明授权

US07888720B2 Semiconductor device including conductive lines with fine line width and method of fabricating the same 有权
标题翻译：包括具有细线宽度的导线的半导体器件及其制造方法
公开(公告)号：US07888720B2
公开(公告)日：2011-02-15
申请号：US11865738
申请日：2007-10-02
申请人： Hyeoung-Won Seo , Byung-Hyug Roh , Seong-Goo Kim , Sang-Min Jeon
发明人： Hyeoung-Won Seo , Byung-Hyug Roh , Seong-Goo Kim , Sang-Min Jeon
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10897 , H01L21/743 , H01L27/105 , H01L27/10882
摘要： A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.
摘要翻译：半导体器件包括半导体衬底，该半导体衬底包括第一芯区域和第二芯区域，第一芯区域和第二芯区域之间插入有单元阵列区域，第一导电线路和延伸到跨越单元阵列区域的第一芯区域的第二导电线，导电线和延伸到跨越单元阵列区域的第二芯区的第四导线，其中第一至第四导线的线宽小于光刻工艺中的分辨率极限。

10. 发明申请

US20080203587A1 SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LINES WITH FINE LINE WIDTH AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有精细线宽度的导电线的半导体器件及其制造方法
公开(公告)号：US20080203587A1
公开(公告)日：2008-08-28
申请号：US11865738
申请日：2007-10-02
申请人： Hyeoung-Won Seo , Byung-Hyug Roh , Seong-Goo Kim , Sang-Min Jeon
发明人： Hyeoung-Won Seo , Byung-Hyug Roh , Seong-Goo Kim , Sang-Min Jeon
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L27/10897 , H01L21/743 , H01L27/105 , H01L27/10882
摘要： A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.
摘要翻译：半导体器件包括半导体衬底，该半导体衬底包括第一芯区域和第二芯区域，第一芯区域和第二芯区域之间插入有单元阵列区域，第一导电线路和延伸到跨越单元阵列区域的第一芯区域的第二导电线，导电线和延伸到跨越单元阵列区域的第二芯区的第四导线，其中第一至第四导线的线宽小于光刻工艺中的分辨率极限。

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