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1. 发明申请

US20070075331A1 INSULATED GATE SEMICONDUCTOR DEVICE 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US20070075331A1
公开(公告)日：2007-04-05
申请号：US11561652
申请日：2006-11-20
申请人： Hiroki WAKIMOTO , Seiji MOMOTA , Masahito OTSUKI
发明人： Hiroki WAKIMOTO , Seiji MOMOTA , Masahito OTSUKI
IPC分类号： H01L29/74
CPC分类号： H01L29/0696 , H01L29/7397
摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.
摘要翻译：公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。它包括通过沟槽分成不同p型基极区的p型基极层。仅在一些p型基区中形成N型源极区。在沟槽IGBT的有源区域中有一个栅极流道。形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。与发射极电气电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关，由式25 <= {N1 /（N1 + N2x100 <= 75。

2. 发明申请

US20100207162A1 VERTICAL AND TRENCH TYPE INSULATED GATE MOS SEMICONDUCTOR DEVICE 有权
标题翻译：垂直和倾斜型绝缘栅MOS半导体器件
公开(公告)号：US20100207162A1
公开(公告)日：2010-08-19
申请号：US12767356
申请日：2010-04-26
申请人： Koh YOSHIKAWA , Hiroki WAKIMOTO , Masahito OTSUKI
发明人： Koh YOSHIKAWA , Hiroki WAKIMOTO , Masahito OTSUKI
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
摘要翻译：提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且选择性地形成在p型沟道区域的表面上的n +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。这使得器件能够实现低导通电阻和增强的关断能力。

3. 发明申请

US20080169526A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20080169526A1
公开(公告)日：2008-07-17
申请号：US11972932
申请日：2008-01-11
申请人： Hiroki WAKIMOTO , Masahito OTSUKI , Takashi SHIIGI
发明人： Hiroki WAKIMOTO , Masahito OTSUKI , Takashi SHIIGI
IPC分类号： H01L29/06
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0696 , H01L29/402 , H01L29/404 , H01L29/66734 , H01L29/7813
摘要： A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal forward blocking voltage capability variation. The edge termination structure has multiple ring-like p-type guard rings, a first insulating film covering the guard rings, and ring-like field plates, provided via the first insulating film atop the guard rings. The field plates have a polysilicon film and a thicker metal film. The polysilicon film is provided on a first guard ring via first insulating film, and a dual field plate made of the polysilicon film and metal film is provided on a second guard ring. The dual field plate is stacked via a second insulating film. The first and second guard rings alternate.
摘要翻译：提供了一种功率半导体器件，其具有采用边缘端接结构中的厚金属膜的场板，即使具有优异的长期正向阻断电压能力可靠性的大的侧蚀刻或蚀刻变化也允许边缘终端结构宽度减小，并且其允许最小的正向阻断电压能力变化。边缘端接结构具有多个环状p型保护环，覆盖保护环的第一绝缘膜和通过护罩顶部上的第一绝缘膜提供的环状场板。场板具有多晶硅膜和较厚的金属膜。多晶硅膜通过第一绝缘膜设置在第一保护环上，并且由多晶硅膜和金属膜制成的双场板设置在第二保护环上。双场板通过第二绝缘膜堆叠。第一和第二保卫环交替出现。

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