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1. 发明授权

US09544133B2 On-the-fly key generation for encryption and decryption 有权
标题翻译：用于加密和解密的即时密钥生成
公开(公告)号：US09544133B2
公开(公告)日：2017-01-10
申请号：US12647459
申请日：2009-12-26
申请人： Sanu K. Mathew , Farhana Sheikh , Ram K. Krishnamurthy , Michael E. Kounavis , Shay Gueron
发明人： Sanu K. Mathew , Farhana Sheikh , Ram K. Krishnamurthy , Michael E. Kounavis , Shay Gueron
IPC分类号： H04L9/00 , H04L9/06 , H04L9/30
CPC分类号： H04L9/0631 , H04L9/3073 , H04L2209/24
摘要： Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described.
摘要翻译：描述了为Galois Field（也称为有限场）加密和/或解密提供实时密钥计算的方法和装置。在一个实施例中，逻辑在第二周期中基于在紧接在第二周期之前的第一周期中生成的先前密码密钥来生成密码密钥。还描述了其它实施例。

2. 发明申请

US20110158403A1 ON-THE-FLY KEY GENERATION FOR ENCRYPTION AND DECRYPTION 有权
标题翻译：用于加密和分解的关键生成器
公开(公告)号：US20110158403A1
公开(公告)日：2011-06-30
申请号：US12647459
申请日：2009-12-26
申请人： Sanu K. Mathew , Farhana Sheikh , Ram K. Krishnamurthy , Michael E. Kounavis , Shay Gueron
发明人： Sanu K. Mathew , Farhana Sheikh , Ram K. Krishnamurthy , Michael E. Kounavis , Shay Gueron
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , H04L9/3073 , H04L2209/24
摘要： Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described.
摘要翻译：描述了为Galois Field（也称为有限场）加密和/或解密提供实时密钥计算的方法和装置。在一个实施例中，逻辑在第二周期中基于在紧接在第二周期之前的第一周期中生成的先前密码密钥来生成密码密钥。还描述了其它实施例。

3. 发明申请

US20150023500A1 APPARATUS AND METHOD FOR SKEIN HASHING 有权
标题翻译：装置和方法进行滑雪
公开(公告)号：US20150023500A1
公开(公告)日：2015-01-22
申请号：US14507427
申请日：2014-10-06
申请人： Farhana Sheikh , Jesse Walker , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Farhana Sheikh , Jesse Walker , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H04L9/08
CPC分类号： H04L9/0861 , H04L9/0618 , H04L9/0625 , H04L9/0631 , H04L9/0637 , H04L9/0643 , H04L9/0816 , H04L2209/125 , H04L2209/24 , H04N1/32277
摘要： Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
摘要翻译：这里描述了用于Skein散列的装置和方法。该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。

4. 发明授权

US08214414B2 Combined set bit count and detector logic 有权
标题翻译：组合位计数和检测器逻辑
公开(公告)号：US08214414B2
公开(公告)日：2012-07-03
申请号：US12242727
申请日：2008-09-30
申请人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
发明人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
IPC分类号： G06F15/00
CPC分类号： G06F7/74 , G06F7/607
摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).
摘要翻译：描述了PopCount和BitScan的合并数据路径。硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。如果选择了BitScan操作，则输入字被编码。压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。

5. 发明申请

US20140229741A1 Dual Composite Field Advanced Encryption Standard Memory Encryption Engine 审中-公开
标题翻译：双复合现场高级加密标准内存加密引擎
公开(公告)号：US20140229741A1
公开(公告)日：2014-08-14
申请号：US13993545
申请日：2011-12-30
申请人： Sanu K. Mathew , Shay Gueron , Ram K. Krishnamurthy
发明人： Sanu K. Mathew , Shay Gueron , Ram K. Krishnamurthy
IPC分类号： G06F21/72 , G06F21/60
CPC分类号： G06F21/72 , G06F21/60 , H04L9/0631 , H04L2209/122
摘要： A different set of polynomials may be selected for encryption and decryption accelerators. That is, different sets of polynomials are used for encryption and decryption, each set being chosen to use less area and deliver more power for a memory encryption engine. This is advantageous in some embodiments since memory read operations are typically more critical and latency sensitive than memory writes.
摘要翻译：可以为加密和解密加速器选择不同的多项式集合。也就是说，不同的多项式组用于加密和解密，每组被选择为使用较少的区域并为存储器加密引擎提供更多的功率。这在一些实施例中是有利的，因为存储器读取操作通常比存储器写入更为关键和延迟敏感。

6. 发明申请

US20100082718A1 COMBINED SET BIT COUNT AND DETECTOR LOGIC 有权
标题翻译：组合设置位计数和检测器逻辑
公开(公告)号：US20100082718A1
公开(公告)日：2010-04-01
申请号：US12242727
申请日：2008-09-30
申请人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
发明人： Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Shay Gueron , Vasantha K. Erraguntla
IPC分类号： G06F7/00
CPC分类号： G06F7/74 , G06F7/607
摘要： A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).
摘要翻译：描述了PopCount和BitScan的合并数据路径。硬件电路包括用于PopCount功能的压缩器树，其由BitScan功能（例如，位扫描前向（BSF）或位扫描反向（BSR））重用。选择器逻辑使压缩器树能够基于微处理器指令对PopCount或BitScan操作的输入字进行操作。如果选择了BitScan操作，则输入字被编码。压缩器树接收输入字，对位进行操作，好像所有位具有相同的重要程度（例如，对于N位输入字，输入字被视为N个一位输入）。压缩器树电路的结果是表示与执行的操作有关的数字的二进制值（PopCount的设置位数，或通过扫描输入字所遇到的第一组位的位位置）。

7. 发明申请

US20150178143A1 USING DARK BITS TO REDUCE PHYSICAL UNCLONABLE FUNCTION (PUF) ERROR RATE WITHOUT STORING DARK BITS LOCATION 有权
标题翻译：使用深色位置减少物理不可靠功能（PUF）错误率，而不会存储明显的位置
公开(公告)号：US20150178143A1
公开(公告)日：2015-06-25
申请号：US14140243
申请日：2013-12-24
申请人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
发明人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F7/00 , G06F7/588 , G06F11/0745 , G11C7/24 , H04L9/3278 , H04L9/34
摘要： Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.
摘要翻译：描述了用于物理不可克隆功能（PUF）组件的暗位掩蔽技术。计算系统包括处理器核心和耦合到处理器核心的安全密钥管理器组件。安全密钥管理器包括PUF组件和耦合到PUF组件的暗位屏蔽电路。暗位掩蔽电路是在暗位窗口期间多次测量PUF分量的PUF值，以检测PUF分量的PUF值是否为暗位。暗位表示PUF组件的PUF值在暗位窗口期间不稳定。当PUF值不是暗位时，暗位屏蔽电路将输出PUF值作为PUF分量的输出PUF位，并且当PUF分量的PUF值为黑暗的一点

8. 发明授权

US09262256B2 Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location 有权
标题翻译：使用暗位来减少物理不可克隆功能（PUF）错误率，而不存储暗位置
公开(公告)号：US09262256B2
公开(公告)日：2016-02-16
申请号：US14140243
申请日：2013-12-24
申请人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
发明人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
IPC分类号： G06F21/00 , H04L29/06 , G06F11/07 , G11C7/24 , G11C7/00 , G06F7/58 , H04L9/34
CPC分类号： G06F11/0793 , G06F7/00 , G06F7/588 , G06F11/0745 , G11C7/24 , H04L9/3278 , H04L9/34
摘要： Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.
摘要翻译：描述了用于物理不可克隆功能（PUF）组件的暗位掩蔽技术。计算系统包括处理器核心和耦合到处理器核心的安全密钥管理器组件。安全密钥管理器包括PUF组件和耦合到PUF组件的暗位屏蔽电路。暗位掩蔽电路是在暗位窗口期间多次测量PUF分量的PUF值，以检测PUF分量的PUF值是否为暗位。暗位表示PUF组件的PUF值在暗位窗口期间不稳定。当PUF值不是暗位时，暗位屏蔽电路将输出PUF值作为PUF分量的输出PUF位，并且当PUF分量的PUF值为黑暗的一点

9. 发明授权

US06404234B1 Variable virtual ground domino logic with leakage control 有权
标题翻译：具有泄漏控制的可变虚拟地面多米诺逻辑
公开(公告)号：US06404234B1
公开(公告)日：2002-06-11
申请号：US09851917
申请日：2001-05-09
申请人： Steven K. Hsu , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A domino logic circuit and method comprise at least two series-connected domino logic stages with each domino logic stage comprising a dynamic stage and a static stage. A variable virtual ground of the first domino logic's static stage is switched to a voltage level below a circuit ground level when a received clock signal and a second domino logic stage's dynamic output are both high, indicating the second domino logic circuit stage is in the evaluation phase.
摘要翻译：多米诺逻辑电路和方法包括至少两个串联连接的多米诺逻辑级，每个多米诺逻辑级包括动态级和静态级。当接收到的时钟信号和第二多米诺逻辑级的动态输出均为高电平时，第一多米诺逻辑逻辑静态级的可变虚拟接地切换到低于电路接地电平的电压电平，表明第二多米诺逻辑电路级处于评估状态相。

10. 发明授权

US08577948B2 Split path multiply accumulate unit 有权
标题翻译：分路径乘积累积单位
公开(公告)号：US08577948B2
公开(公告)日：2013-11-05
申请号：US12886012
申请日：2010-09-20
申请人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
发明人： Suresh Srinivasan , Rajaraman Ramanarayanan , Sanu K. Mathew , Ram K. Krishnamurthy , Vasantha K. Erraguntla
IPC分类号： G06F7/483
CPC分类号： G06F9/3893 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036
摘要： In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，如果第一和第二操作数的至少一部分与第三操作数之间的差小于阈值，则处理器包括具有第一路径以处理指令的执行的乘法累加（MAC）单元，以及如果差值大于阈值，则处理指令执行的第二路径。基于该差异，第三操作数的至少一部分将被提供给MAC单元的乘法器或第二路径的压缩器。描述和要求保护其他实施例。

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