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1. 发明授权

US08923510B2 Method and apparatus for efficiently implementing the advanced encryption standard 有权
标题翻译：有效实施高级加密标准的方法和装置
公开(公告)号：US08923510B2
公开(公告)日：2014-12-30
申请号：US11966658
申请日：2007-12-28
申请人： Shay Gueron , Michael E. Kounavis , Ram Krishnamurthy , Sanu K. Mathew
发明人： Shay Gueron , Michael E. Kounavis , Ram Krishnamurthy , Sanu K. Mathew
IPC分类号： H04L9/00 , G06F7/00
CPC分类号： H04L9/0631 , G06F7/00 , G06F9/30007 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30196 , G06F9/3887 , G06F21/602 , H04L2209/34
摘要： Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256). In an embodiment of inverse-columns-mixing, the 16 byte values are converted from a polynomial representation in GF(256) to a polynomial representation in GF((24)2). A four-by-four matrix is applied to the transformed polynomial representation in GF((24)2) to implement the inverse-columns-mixing.
摘要翻译：公开了高级加密标准（AES）加密和解密过程的实现。在S盒处理的一个实施例中，转换16字节值的块，每个字节值从GF（256）中的多项式表示转换为GF（（22）4）中的多项式表示。对于GF（（22）4）中的每个对应多项式表示，计算GF（（22）4）中的乘法逆多项式表示。最后，对GF（（22）4）中的相应的乘法逆多项式表示进行转换，并应用仿射变换以在GF（256）中生成对应的多项式表示。在S盒处理的替代实施例中，计算多项式表示的幂并在GF（256）中相乘，以在GF（256）中生成乘法逆多项式表示。在反列混合的实施例中，将16字节值从GF（256）中的多项式表示转换为GF（（24）2）中的多项式表示。将四乘四矩阵应用于GF（（24）2）中的变换多项式表示，以实现反列混合。

2. 发明申请

US20090172068A1 METHOD AND APPARATUS FOR EFFICIENTLY IMPLEMENTING THE ADVANCED ENCRYPTION STANDARD 有权
标题翻译：有效执行高级加密标准的方法和设备
公开(公告)号：US20090172068A1
公开(公告)日：2009-07-02
申请号：US11966658
申请日：2007-12-28
申请人： MICHAEL E. KOUNAVIS , Shay Gueron , Ram Krishnamurthy , Sanu K. Mathew
发明人： MICHAEL E. KOUNAVIS , Shay Gueron , Ram Krishnamurthy , Sanu K. Mathew
IPC分类号： G06F7/38
CPC分类号： H04L9/0631 , G06F7/00 , G06F9/30007 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30196 , G06F9/3887 , G06F21/602 , H04L2209/34
摘要： Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256). In an embodiment of inverse-columns-mixing, the 16 byte values are converted from a polynomial representation in GF(256) to a polynomial representation in GF((24)2). A four-by-four matrix is applied to the transformed polynomial representation in GF((24)2) to implement the inverse-columns-mixing.
摘要翻译：公开了高级加密标准（AES）加密和解密过程的实现。在S盒处理的一个实施例中，转换16字节值的块，每个字节值从GF（256）中的多项式表示转换为GF（（22）4）中的多项式表示。对于GF（（22）4）中的每个对应多项式表示，计算GF（（22）4）中的乘法逆多项式表示。最后，对GF（（22）4）中的相应的乘法逆多项式表示进行转换，并应用仿射变换以在GF（256）中生成对应的多项式表示。在S盒处理的替代实施例中，计算多项式表示的幂并在GF（256）中相乘，以在GF（256）中生成乘法逆多项式表示。在反列混合的实施例中，将16字节值从GF（256）中的多项式表示转换为GF（（24）2）中的多项式表示。将四乘四矩阵应用于GF（（24）2）中的变换多项式表示，以实现反列混合。

3. 发明申请

US20140201540A1 SECURE KEY STORAGE USING PHYSICALLY UNCLONABLE FUNCTIONS 有权
标题翻译：使用物理不可靠函数确保关键存储
公开(公告)号：US20140201540A1
公开(公告)日：2014-07-17
申请号：US13996544
申请日：2011-12-29
申请人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
发明人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
IPC分类号： H04L9/08
CPC分类号： H04L9/0891 , G09C1/00 , H04L9/0822 , H04L9/0861 , H04L9/0866 , H04L9/0894 , H04L2209/12
摘要： Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor.
摘要翻译：本文公开的一些实施例提供了用于向集成电路/处理器供应密钥的技术和布置处理器可以包括物理上不可克隆的功能组件，其可以至少基于处理器的至少一个物理特性来生成唯一的硬件密钥。硬件密钥可用于加密诸如秘密密钥的密钥。加密密钥可以存储在处理器的存储器中。可以验证加密的密钥。可以通过通信地隔离处理器的至少一个组件来保护密钥的完整性。

4. 发明授权

US07131055B2 Fast bit-parallel Viterbi decoder add-compare-select circuit 失效
标题翻译：快速位并行维特比解码器加比较选择电路
公开(公告)号：US07131055B2
公开(公告)日：2006-10-31
申请号：US10372121
申请日：2003-02-25
申请人： Sanu K. Mathew , Ram Krishnamurthy , Hoang Q. Dao
发明人： Sanu K. Mathew , Ram Krishnamurthy , Hoang Q. Dao
IPC分类号： H03M13/03
CPC分类号： H03M13/6502 , H03M13/4107
摘要： A Viterbi decoder includes an ACS unit that performs state metric updates for every symbol cycle. State metric updates involve adding the state metrics corresponding to a likely input symbol to the respective branch matrix, comparing the results of the additions to determine which is smaller, and selecting the smaller result for the next state metric. The ACS unit includes two parallel adders followed by a parallel comparator that generates a multiplexer-select signal. The outputs of the parallel adders are input into a multiplexer and the multiplexer-select signal is input into the multiplexer for a decision.
摘要翻译：维特比解码器包括对每个符号周期执行状态度量更新的ACS单元。状态度量更新涉及将对应于可能的输入符号的状态量度相加到相应的分支矩阵，比较添加的结果以确定哪个更小，并为下一状态度量选择较小的结果。 ACS单元包括两个并行加法器，其后是并行比较器，其产生多路选择器选择信号。并行加法器的输出被输入到多路复用器中，并且多路复用器选择信号被输入到多路复用器中用于决定。

5. 发明授权

US06781892B2 Active leakage control in single-ended full-swing caches 有权
标题翻译：单端全频高速缓存中的主动泄漏控制
公开(公告)号：US06781892B2
公开(公告)日：2004-08-24
申请号：US10033337
申请日：2001-12-26
申请人： Steven K. Hsu , Sanu K. Mathew , Ram Krishnamurthy
发明人： Steven K. Hsu , Sanu K. Mathew , Ram Krishnamurthy
IPC分类号： G11C700
CPC分类号： G11C7/12
摘要： A single-ended, full-swing dynamic cache having memory cells grouped into memory groups, where for each memory group one or more foot transistors connect to various memory cells within the memory group. Using a foot transistor reduces sub-threshold leakage current when the memory cells connected to the foot transistor are not being read.
摘要翻译：具有分组到存储器组中的存储器单元的单端，全摆幅动态高速缓存，其中对于每个存储器组，一个或多个脚晶体管连接到存储器组内的各种存储器单元。当连接到脚晶体管的存储单元未被读取时，使用脚晶体管可以减小子阈值漏电流。

6. 发明授权

US09544141B2 Secure key storage using physically unclonable functions 有权
标题翻译：使用物理不可克隆功能保护密钥存储
公开(公告)号：US09544141B2
公开(公告)日：2017-01-10
申请号：US13996544
申请日：2011-12-29
申请人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
发明人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
IPC分类号： H04L29/06 , H04L9/08
CPC分类号： H04L9/0891 , G09C1/00 , H04L9/0822 , H04L9/0861 , H04L9/0866 , H04L9/0894 , H04L2209/12
摘要： Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor.
摘要翻译：本文公开的一些实施例提供了用于向集成电路/处理器供应密钥的技术和布置。处理器可以包括物理上不可克隆的功能组件，其可以至少基于处理器的至少一个物理特性来生成唯一的硬件密钥。硬件密钥可用于加密诸如秘密密钥的密钥。加密密钥可以存储在处理器的存储器中。可以验证加密的密钥。可以通过通信地隔离处理器的至少一个组件来保护密钥的完整性。

7. 发明授权

US07477171B2 Binary-to-BCD conversion 有权
标题翻译：二进制到BCD转换
公开(公告)号：US07477171B2
公开(公告)日：2009-01-13
申请号：US11729191
申请日：2007-03-27
申请人： Sanu K. Mathew , Ram Krishnamurthy
发明人： Sanu K. Mathew , Ram Krishnamurthy
IPC分类号： H03M7/04
CPC分类号： H03M7/12
摘要： Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.
摘要翻译：本文公开了将二进制值转换为BCD值的电路和方法的各种实施例。

8. 发明申请

US20080238736A1 BINARY-TO-BCD CONVERSION 有权
标题翻译：二进制转换
公开(公告)号：US20080238736A1
公开(公告)日：2008-10-02
申请号：US11729191
申请日：2007-03-27
申请人： Sanu K. Mathew , Ram Krishnamurthy
发明人： Sanu K. Mathew , Ram Krishnamurthy
IPC分类号： H03M7/12
CPC分类号： H03M7/12
摘要： Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.
摘要翻译：本文公开了将二进制值转换为BCD值的电路和方法的各种实施例。

9. 发明授权

US07380099B2 Apparatus and method for an address generation circuit 有权
标题翻译：地址生成电路的装置和方法
公开(公告)号：US07380099B2
公开(公告)日：2008-05-27
申请号：US10956164
申请日：2004-09-30
申请人： Sanu K. Mathew , Mark A. Anders , Sarvesh H. Kulkarni , Ram Krishnamurthy
发明人： Sanu K. Mathew , Mark A. Anders , Sarvesh H. Kulkarni , Ram Krishnamurthy
IPC分类号： G06F12/00
CPC分类号： G06F7/507 , G06F7/508
摘要： A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.
摘要翻译：一种用于地址产生电路的方法和装置。在一个实施例中，该方法包括计算由多个逻辑地址分量形成的传播信号和生成信号的预定位数的至少一组的进位。一旦计算了进位，则为逻辑0进位和逻辑1进位产生多个条件和。随后，从多个条件和中选出一个和，以在第二阶段中的第一阶段的逻辑地址分量和有效地址的第二部分中形成有效地址的第一部分。在一个实施例中，根据一个实施例，使用产生四分之一载波的完全动态的高性能稀疏树加法器电路来形成地址生成电路。描述和要求保护其他实施例。

10. 发明授权

US08855302B2 Apparatus and method for Skein hashing 有权
标题翻译： Skein散列的装置和方法
公开(公告)号：US08855302B2
公开(公告)日：2014-10-07
申请号：US13165269
申请日：2011-06-21
申请人： Farhana Sheikh , Jesse Walker , Sanu K. Mathew , Ram Krishnamurthy
发明人： Farhana Sheikh , Jesse Walker , Sanu K. Mathew , Ram Krishnamurthy
IPC分类号： H04L9/00 , H04L9/06 , H04N1/32
CPC分类号： H04L9/0861 , H04L9/0618 , H04L9/0625 , H04L9/0631 , H04L9/0637 , H04L9/0643 , H04L9/0816 , H04L2209/125 , H04L2209/24 , H04N1/32277
摘要： Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
摘要翻译：这里描述了用于Skein散列的装置和方法。该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。

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