专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07447956B2 Method and apparatus for testing data steering logic for data storage having independently addressable subunits 有权
标题翻译：用于测试具有独立可寻址子单元的数据存储的数据转向逻辑的方法和装置
公开(公告)号：US07447956B2
公开(公告)日：2008-11-04
申请号：US11367959
申请日：2006-03-03
申请人： Lakshmikant Mamileti , Anand Krishnamurthy , Clint Wayne Mumford , Sanjay B Patel
发明人： Lakshmikant Mamileti , Anand Krishnamurthy , Clint Wayne Mumford , Sanjay B Patel
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/022 , G11C29/1201 , G11C29/44 , G11C29/4401 , G11C2029/1208
摘要： Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.
摘要翻译：通过为存储器阵列存储位置的每个可寻址子单元提供数据总线通道来测试存储器阵列的I / O中的读写数据转向逻辑。每个总线通道连接到比较器的数据输入。 BIST控制器通过写入指导逻辑将测试模式写入存储器，并并行读取测试模式以测试写入转向逻辑。 BIST控制器将测试模式并行地写入存储器，并通过读取转向逻辑读取测试模式，以测试读取转向逻辑。在这两种情况下，专用于每个总线通道的单独的比较器验证子数据在数据总线通道和存储器存储位置子单元之间正确移位。比较器在正常操作期间被有效地禁用，以防止逻辑门切换。

2. 发明申请

US20070220378A1 Method and apparatus for testing data steering logic for data storage having independently addressable subunits 有权
标题翻译：用于测试具有独立可寻址子单元的数据存储的数据转向逻辑的方法和装置
公开(公告)号：US20070220378A1
公开(公告)日：2007-09-20
申请号：US11367959
申请日：2006-03-03
申请人： Lakshmikant Mamileti , Anand Krishnamurthy , Clint Wayne Mumford , Sanjay Patel
发明人： Lakshmikant Mamileti , Anand Krishnamurthy , Clint Wayne Mumford , Sanjay Patel
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/022 , G11C29/1201 , G11C29/44 , G11C29/4401 , G11C2029/1208
摘要： Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.
摘要翻译：通过为存储器阵列存储位置的每个可寻址子单元提供数据总线通道来测试存储器阵列的I / O中的读写数据转向逻辑。每个总线通道连接到比较器的数据输入。 BIST控制器通过写入指导逻辑将测试模式写入存储器，并并行读取测试模式以测试写入转向逻辑。 BIST控制器将测试模式并行地写入存储器，并通过读取转向逻辑读取测试模式，以测试读取转向逻辑。在这两种情况下，专用于每个总线通道的单独的比较器验证子数据在数据总线通道和存储器存储位置子单元之间正确移位。比较器在正常操作期间被有效地禁用，以防止逻辑门切换。

3. 发明申请

US20070208968A1 At-speed multi-port memory array test method and apparatus 审中-公开
标题翻译：高速多端口内存阵列测试方法和装置
公开(公告)号：US20070208968A1
公开(公告)日：2007-09-06
申请号：US11365648
申请日：2006-03-01
申请人： Anand Krishnamurthy , Clint Mumford , Lakshmikant Mamileti , Sanjay Patel
发明人： Anand Krishnamurthy , Clint Mumford , Lakshmikant Mamileti , Sanjay Patel
IPC分类号： G11C29/00
CPC分类号： G11C29/34 , G11C8/16
摘要： A multi-port memory array is tested by simultaneously writing data to the array via two or more write ports, and/or simultaneously reading data from the array via two or more read ports, at the processor operating frequency. Comparing the data read from the array to that written to the array may be performed sequentially or in parallel. Comparator circuits are effectively disabled during normal processor operations. By simultaneously writing and/or reading data via multiple ports, latent electrical marginalities may be exposed. In addition, writing test patterns using multiple write ports and reading the patterns using multiple read ports significantly reduces test time during semiconductor manufacturing tests.
摘要翻译：多端口存储器阵列通过经由两个或多个写入端口同时将数据写入阵列，和/或在处理器工作频率下经由两个或更多个读取端口同时从阵列读取数据进行测试。将从阵列读取的数据与写入阵列的数据进行比较可以顺序或并行执行。在正常的处理器操作期间，比较器电路被有效地禁用。通过同时通过多个端口写入和/或读取数据，可能会暴露潜在的电气边界。此外，使用多个写入端口编写测试模式并使用多个读取端口读取模式可大大减少半导体制造测试期间的测试时间。

4. 发明申请

US20080115026A1 Method and Apparatus for Scheduling BIST Routines 失效
标题翻译：用于调度BIST例程的方法和装置
公开(公告)号：US20080115026A1
公开(公告)日：2008-05-15
申请号：US11553609
申请日：2006-10-27
申请人： James Norris Dieffenderfer , Anand Krishnamurthy , Clint Wayne Mumford , Jason Lawrence Panavich , Ketan Vitthal Patel , Ravi Rajagopalan , Thomas Philip Speier
发明人： James Norris Dieffenderfer , Anand Krishnamurthy , Clint Wayne Mumford , Jason Lawrence Panavich , Ketan Vitthal Patel , Ravi Rajagopalan , Thomas Philip Speier
IPC分类号： G01R31/28
CPC分类号： G01R31/31707 , G01R31/3187
摘要： The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.
摘要翻译：硬编码和/或准可编程测试图案的预定顺序的内容和顺序可以在内置自检（BIST）程序期间改变。因此，获得后期设计完成的知识可能反映在BIST程序中执行的可用测试的选择和排列。在一个实施例中，在BIST程序期间通过接收测试序列的测试排序信息并按照测试顺序信息所示的顺序执行测试序列来执行硬编码和/或准可编程测试序列。相应的BIST电路包括存储元件和状态机。存储元件被配置为存储测试序列的测试排序信息。状态机被配置为按照测试顺序信息指示的顺序执行测试序列。

5. 发明申请

US20080109691A1 Method and Apparatus for Executing a BIST Routine 审中-公开
标题翻译：执行BIST程序的方法和装置
公开(公告)号：US20080109691A1
公开(公告)日：2008-05-08
申请号：US11553582
申请日：2006-10-27
申请人： James Norris Dieffenderfer , Anand Krishnamurthy , Clint Wayne Mumford , Thomas Philip Speier
发明人： James Norris Dieffenderfer , Anand Krishnamurthy , Clint Wayne Mumford , Thomas Philip Speier
IPC分类号： G01R31/28
CPC分类号： G01R31/3187
摘要： During a Built-In Self-Test (BIST) routine, execution of a sequence of tests is re-initiated after a corrective action is taken starting with the test having the highest re-ordered priority. The test having the highest re-ordered priority corresponds to a test in a sequence of tests that detected the error corresponding to the corrective action taken or a related test in the case where the test that detected the error is dependent upon results generated by the related test. According to one embodiment, a BIST routine is executed by initiating execution of a sequence of tests configured to detect errors and, after a corrective action is taken in response to one or more of the errors being detected, re-initiating execution of the sequence of tests starting with the test that detected the error corresponding to the corrective action most recently taken.
摘要翻译：在内置自检（BIST）例程中，在从重新排序的优先级最高的测试开始执行纠正措施后，重新启动一系列测试的执行。具有最高重排优先级的测试对应于检测到所采取的纠正措施的错误或相关测试的测试序列中的测试，其中检测到错误的测试取决于相关产生的结果测试。根据一个实施例，通过启动被配置为检测错误的测试序列的执行来执行BIST程序，并且在响应于被检测到的一个或多个错误而采取纠正措施之后，重新开始执行测试开始时，检测到与最近采取的纠正措施相对应的错误。

6. 发明授权

US08499208B2 Method and apparatus for scheduling BIST routines 失效
标题翻译：调度BIST例程的方法和装置
公开(公告)号：US08499208B2
公开(公告)日：2013-07-30
申请号：US11553609
申请日：2006-10-27
申请人： James Norris Dieffenderfer , Anand Krishnamurthy , Clint Wayne Mumford , Jason Lawrence Panavich , Ketan Vitthal Patel , Ravi Rajagopalan , Thomas Philip Speier
发明人： James Norris Dieffenderfer , Anand Krishnamurthy , Clint Wayne Mumford , Jason Lawrence Panavich , Ketan Vitthal Patel , Ravi Rajagopalan , Thomas Philip Speier
IPC分类号： G01R31/28
CPC分类号： G01R31/31707 , G01R31/3187
摘要： The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.
摘要翻译：硬编码和/或准可编程测试图案的预定顺序的内容和顺序可以在内置自检（BIST）程序期间改变。因此，获得后期设计完成的知识可能反映在BIST程序中执行的可用测试的选择和排列。在一个实施例中，在BIST程序期间，通过接收测试序列的测试排序信息并按测试顺序信息指示的顺序执行测试序列来执行硬编码和/或准可编程测试序列。相应的BIST电路包括存储元件和状态机。存储元件被配置为存储测试序列的测试排序信息。状态机被配置为按照测试顺序信息所示的顺序执行测试序列。

7. 发明授权

US09584614B2 Method and system for migrating an interface 有权
标题翻译：用于迁移界面的方法和系统
公开(公告)号：US09584614B2
公开(公告)日：2017-02-28
申请号：US14593482
申请日：2015-01-09
申请人： Sankara Subramanian Palanisamy , Anand Krishnamurthy
发明人： Sankara Subramanian Palanisamy , Anand Krishnamurthy
IPC分类号： H04L29/08
CPC分类号： H04L67/2809 , H04L67/2842 , H04L67/34
摘要： Embodiments of this disclosure relate to methods and systems for migrating an interface. One disclosed method may include discovering types associated with a plurality of source middleware nodes, and discovering one or more links between them. It may include mapping the plurality of source middleware nodes to nodes of a global middleware model based on the types, wherein the global middleware model comprises a format interoperable between a source middleware platform and a target middleware platform. It may further include establishing one or more links between the nodes of the global middleware model based on the one or more links between the plurality of source middleware nodes. It may also include migrating the nodes of the global middleware model and the one or more links between the nodes of the global middleware model to the target middleware platform based on mapping the global middleware model to the target middleware platform.
摘要翻译：本公开的实施例涉及用于迁移接口的方法和系统。一种公开的方法可以包括发现与多个源中间件节点相关联的类型，并且发现它们之间的一个或多个链路。它可以包括基于类型将多个源中间件节点映射到全球中间件模型的节点，其中全球中间件模型包括可在源中间件平台和目标中间件平台之间互操作的格式。其还可以包括基于多个源中间件节点之间的一个或多个链路在全球中间件模型的节点之间建立一个或多个链路。它还可以包括将全球中间件模型的节点和全球中间件模型的节点之间的一个或多个链路迁移到目标中间件平台，基于将全球中间件模型映射到目标中间件平台。

8. 发明申请

US20130085864A1 MOBILE CONTENT DELIVERY 审中-公开
标题翻译：移动内容交付
公开(公告)号：US20130085864A1
公开(公告)日：2013-04-04
申请号：US13251657
申请日：2011-10-03
申请人： Hassan Ahmed , Anand Krishnamurthy , Terry Durand , Tim Mortsolf , Paul Sherer
发明人： Hassan Ahmed , Anand Krishnamurthy , Terry Durand , Tim Mortsolf , Paul Sherer
IPC分类号： G06F15/16 , G06Q30/02 , H04W88/02
CPC分类号： H04W4/18 , G06Q30/04 , H04W8/18
摘要： Methods and apparatus, including computer program products, for mobile content delivery. A method includes, in a mobile network, maintaining a database of mobile subscriber information for mobile subscribers derived from the mobile network, receiving a request for content from a mobile subscriber, loading the requested content, processing the requested content in conjunction with mobile subscriber information in the database of mobile subscriber information, and delivering the processed requested content to the mobile subscriber.
摘要翻译：方法和设备，包括计算机程序产品，用于移动内容传送。一种方法包括在移动网络中维护从移动网络导出的用于移动用户的移动用户信息的数据库，从移动用户接收对内容的请求，加载所请求的内容，结合移动用户信息处理所请求的内容在移动用户信息的数据库中，并将处理过的所请求的内容传送给移动用户。

9. 发明授权

US08327377B2 Detecting, logging and tracking component dependencies in web service transactions 有权
标题翻译：检测，记录和跟踪Web服务事务中的组件依赖关系
公开(公告)号：US08327377B2
公开(公告)日：2012-12-04
申请号：US12433593
申请日：2009-04-30
申请人： Anand Krishnamurthy , Stewart Thain , Todd Rader , Michael Goulet
发明人： Anand Krishnamurthy , Stewart Thain , Todd Rader , Michael Goulet
IPC分类号： G06F9/54 , G06F9/44
CPC分类号： G06F11/3612 , G06F11/3495 , G06F11/3664 , G06F2201/865
摘要： Relationships between components in an application and the services they provide are identified, including redundant caller-callee sequences. Specific components of interest are instrumented to obtain data when they execute. Data structures are created which identify the components and their dependencies on one other. To avoid excessive overhead costs, redundant dependencies are identified. A dependency data structure can be provided for each unique dependency. When repeated instances of a dependency are detected, the associated dependency data structure can be augmented with correlation data of the repeated instances, such as transaction identifiers and sequence identifiers. Sequence identifiers identify an order in which a component is called. A flag can be used to force the creation of a new dependency data structure, and a calling component's name can be used instead of a sequence identifier. Agents report the dependency data structures to a manager to provide graph data in a user interface.
摘要翻译：识别应用程序中的组件与它们提供的服务之间的关系，包括冗余的调用方调用程序序列。感兴趣的特定组件在执行时被用来获取数据。创建数据结构，它们标识组件及其依赖关系。为了避免过多的间接成本，确定了冗余依赖关系。可以为每个唯一的依赖关系提供依赖关系数据结构。当检测到依赖关系的重复实例时，可以利用重复实例的相关数据（诸如事务标识符和序列标识符）来增强相关联的依赖关系数据结构。序列标识符标识组件被调用的顺序。可以使用标志强制创建新的依赖关系数据结构，并且可以使用调用组件的名称而不是序列标识符。代理将依赖数据结构报告给管理器，以在用户界面中提供图形数据。

10. 发明授权

US07466323B2 Key image note display and annotation system and method 有权
标题翻译：关键图像笔记显示和注释系统及方法
公开(公告)号：US07466323B2
公开(公告)日：2008-12-16
申请号：US10453559
申请日：2003-06-03
申请人： Anand Krishnamurthy , Muthu Venkatesh Muthuraj , Benjamin D. Novatzky , Steven Lawrence Fors
发明人： Anand Krishnamurthy , Muthu Venkatesh Muthuraj , Benjamin D. Novatzky , Steven Lawrence Fors
IPC分类号： G09G5/377 , G06T11/60
CPC分类号： A61B6/463 , A61B6/00 , A61B6/468 , H04N2201/3266 , H04N2201/3273
摘要： A method and apparatus for displaying annotations on a digital image such that the viewing area is simplified and maximized. Abbreviated reason codes are employed, thereby increasing the number of annotations that may be displayed concurrently with an image and reducing the obtrusiveness of the annotations. The abbreviated reason codes may provide information to viewers about the significance of the image. Viewers may configure where the annotations are displayed and may associate priorities with the reason codes such that annotations of interest may be displayed more prominently or accessibly. Likewise, text descriptions associated with an annotation may be hidden until requested by a viewer. In instances where the number of annotations exceeds some configurable threshold, the excess annotations may be hidden unless requested.
摘要翻译：一种用于在数字图像上显示注释使得观看区域被简化和最大化的方法和装置。采用缩写原因代码，从而增加可能与图像同时显示的注释数量，并降低注释的含义。缩写原因代码可以向观众提供关于图像的重要性的信息。查看者可以配置显示注释的位置，并且可以将优先级与原因代码相关联，使得可以更显着地或可访问地显示感兴趣的注释。类似地，与注释相关联的文本描述可以被隐藏，直到由观看者请求。在注释数超过某个可配置阈值的情况下，除非请求，否则可能会隐藏多余的注释。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式