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    • 3. 发明授权
    • Tailored field in multigate FETS
    • 多场FET中的定制领域
    • US6037830A
    • 2000-03-14
    • US074770
    • 1998-05-08
    • Samson Mil'shteinSergey NabokinShixian Sui
    • Samson Mil'shteinSergey NabokinShixian Sui
    • H03K17/0412H03K17/687H03K17/785
    • H03K17/687H03K17/04123
    • A uniform tailored electrical field in a multigate field effect D-mode transistor is automatically provided by a feedback circuit which couples drain bias voltages to the gates of a multigate transistor to bias the gates incrementally such that the highest voltage is applied to the gate nearest the drain while the lowest voltage is applied to the gate nearest the source. E-mode multigate FET's carry higher gate voltage on the gate close to the source compared to a gate voltage on a last gate, located close to the drain. The proper distribution of gate voltages improves the transconductance G.sub.m of the transistor and decreases gate capacitance C.sub.gs, which increases the speed of operation of a multigate FETs.
    • 多重场效应D模式晶体管中的均匀定制的电场由反馈电路自动提供,反馈电路将漏极偏置电压耦合到多晶硅晶体管的栅极,以逐渐偏置栅极,使得最高电压施加到最接近 漏极,而最低电压施加到最靠近源极的栅极。 与靠近漏极的最后一个栅极上的栅极电压相比,E模式多栅极FET在靠近源极的栅极上承载更高的栅极电压。 栅极电压的适当分布提高了晶体管的跨导Gm并降低了栅极电容Cgs,这增加了多栅FET的工作速度。
    • 5. 发明授权
    • Transistor device including buried source
    • 晶体管器件包括埋地源
    • US06833571B1
    • 2004-12-21
    • US10188733
    • 2002-07-02
    • Samson Mil'shteinCarlos A. Gil
    • Samson Mil'shteinCarlos A. Gil
    • H01L2976
    • H01L29/8122H01L29/0891H01L29/41725
    • A transistor device includes a gate region disposed adjacent to a semiconductor substrate such that a low impedance channel is formed between a source region and drain region of a transistor device when a voltage is applied to its gate. The drain region of the device can be disposed aside the gate region on a common surface of the semiconductor substrate. The source region of the device also can be disposed adjacent to the substrate but on a side of the semiconductor substrate opposing the drain and/or gate regions. Based on this topology, a transistor device can be fabricated with a buried source to enhance its operating characteristics such as switching speed.
    • 晶体管器件包括与半导体衬底相邻设置的栅极区域,使得当向其栅极施加电压时,在晶体管器件的源极区域和漏极区域之间形成低阻抗沟道。 器件的漏极区域可以放置在半导体衬底的公共表面上的栅极区域的旁边。 器件的源极区域也可以被布置成与衬底相邻,但是在与漏极和/或栅极区域相对的半导体衬底的一侧上。 基于这种拓扑结构,可以用埋入源制造晶体管器件,以增强其工作特性,例如开关速度。