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1. 发明申请

WO2008121206A1 APPARATUS AND METHOD COMBINING LOWER-ENDURANCE/PERFORMANCE AND HIGHER-ENDURANCE/PERFORMANCE INFORMATION STORAGE TO SUPPORT DATA PROCESSING 审中-公开
标题翻译：设备和方法组合低维护性能和高耐久性/性能信息存储来支持数据处理
公开(公告)号：WO2008121206A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/003112
申请日：2008-03-07
申请人： SANDISK CORPORATION , DUNLOP, Neil, A. , GOROBETS, Sergey, A. , KEALY, Kevin, P.
发明人： DUNLOP, Neil, A. , GOROBETS, Sergey, A. , KEALY, Kevin, P.
IPC分类号： G11C11/00 , G11C16/34
CPC分类号： G11C16/349 , G06F3/0616 , G06F3/0659 , G06F3/068 , G06F12/0246 , G06F12/08 , G06F12/121 , G11C2216/26
摘要： An information storage arrangement that combines higher-endurance (or performance) storage with lower-endurance (or performance) storage is managed in a manner that makes judicious use of the lower-endurance (or performance) storage. It is therefore possible to exploit the economic advantage associated with lower- endurance (or performance) storage, while also avoiding storage capacity losses that would otherwise be associated with lower-endurance (or performance) storage.
摘要翻译：将更高耐用性（或性能）存储与低耐久性（或性能）存储结合在一起的信息存储装置以明智地使用低寿命（或性能）存储的方式进行管理。因此，可以利用与低耐久性（或性能）存储相关的经济优势，同时也避免与低寿命（或性能）存储相关的存储容量损失。

2. 发明申请

WO2007079358A3 METHOD AND SYSTEM FOR ACCESSING NON-VOLATILE STORAGE DEVICES 审中-公开
标题翻译：用于接入非易失存储器件的方法和系统
公开(公告)号：WO2007079358A3
公开(公告)日：2008-01-03
申请号：PCT/US2006062340
申请日：2006-12-19
申请人： SANDISK CORP , GOROBETS SERGEY A , SINCLAIR ALAN W
发明人： GOROBETS SERGEY A , SINCLAIR ALAN W
IPC分类号： G06F17/30
CPC分类号： G06F17/30218
摘要： A mass storage memory system is provided. The memory system includes, re-programmable non-volatile memory cells arranged in a plurality of blocks of memory cells; and a controller that is adapted to receive data via a first interface, and a second interface, and data received via the first interface and the second interface is accessible via the first interface and the second interface even if a file name for the data is not provided by a host system or before a write operation is complete. The first interface is a file based interface and the second interface is a logical interface.
摘要翻译：提供大容量存储存储器系统。存储器系统包括布置在存储器单元的多个块中的可重新编程的非易失性存储器单元; 以及适于经由第一接口和第二接口接收数据的控制器，以及经由所述第一接口和所述第二接口接收的数据可以经由所述第一接口和所述第二接口访问，即使所述数据的文件名不是由主机系统提供或在写操作完成之前。第一个接口是一个基于文件的接口，第二个接口是一个逻辑接口。

3. 发明申请

WO2009021176A2 URGENCY AND TIME WINDOW MANIPULATION TO ACCOMMODATE UNPREDICTABLE MEMORY OPERATIONS 审中-公开
公开(公告)号：WO2009021176A2
公开(公告)日：2009-02-12
申请号：PCT/US2008072609
申请日：2008-08-08
申请人： SANDISK CORP , TRINGALI JAMES J , GOROBETS SERGEY A , TRAISTER SHAI , ATAKLTI YOSIEF
发明人： TRINGALI JAMES J , GOROBETS SERGEY A , TRAISTER SHAI , ATAKLTI YOSIEF
IPC分类号： G06F13/16 , G06F11/10
CPC分类号： G06F13/161 , Y02D10/14
摘要： The variable latency associated with flash memory due to background data integrity operations is managed in order to allow the flash memory to be used in isochronous systems. A system processor is notified regularly of the nature and urgency of requests for time to ensure data integrity. Minimal interruptions of system processing are achieved and operation is ensured in the event of a power interruption.

4. 发明申请

WO2007076378A3 DUAL MODE ACCESS FOR NON-VOLATILE STORAGE DEVICES 审中-公开
标题翻译：用于非易失性存储设备的双模式访问
公开(公告)号：WO2007076378A3
公开(公告)日：2007-08-16
申请号：PCT/US2006062341
申请日：2006-12-19
申请人： SANDISK CORP , SINCLAIR ALAN W , GOROBETS SERGEY A
发明人： SINCLAIR ALAN W , GOROBETS SERGEY A
IPC分类号： G06F3/06 , G06F12/00
CPC分类号： G06F3/0643 , G06F3/0605 , G06F3/0679
摘要： Method and mass storage memory system is provided. The system includes, re-programmable non-volatile memory cells, the memory cells being arranged in a plurality of blocks that are erasable together; and a controller including a microprocessor that is adapted to receive files of data identified by unique identifiers via a first interface and the controller causes a received data file to be stored in one or more memory blocks; and the controller receives data identified by logical addresses via a second interface and stores the received data in one or more memory blocks, wherein data written via the first interface is indexed using the unique identifiers so that data is accessible via the second interface or the first interface; and data received via the second interface is indexed so that data can be accessed via the first interface or the second interface.
摘要翻译：提供方法和大容量存储器存储系统。该系统包括可重新编程的非易失性存储器单元，存储器单元被布置在可一起擦除的多个块中; 以及包括微处理器的控制器，所述微处理器适于经由第一接口接收由唯一标识符标识的数据文件，并且所述控制器使接收到的数据文件存储在一个或多个存储块中; 并且所述控制器经由第二接口接收由逻辑地址标识的数据并且将所接收的数据存储在一个或多个存储块中，其中使用所述唯一标识符对经由所述第一接口写入的数据编索引以使得可以经由所述第二接口或所述第一接口接口; 并且经由第二接口接收到的数据被索引，使得可以经由第一接口或第二接口访问数据。

5. 发明申请

WO2011081990A1 ERASE COMMAND CACHING TO IMPROVE ERASE PERFORMANCE ON FLASH MEMORY 审中-公开
标题翻译：删除命令缓存以提高闪速存储器的擦除性能
公开(公告)号：WO2011081990A1
公开(公告)日：2011-07-07
申请号：PCT/US2010/061092
申请日：2010-12-17
申请人： SANDISK CORPORATION , HUTCHISON, Neil, D. , BENNETT, Alan, D. , GOROBETS, Sergey, A. , SPROUSE, Steven, T.
发明人： HUTCHISON, Neil, D. , BENNETT, Alan, D. , GOROBETS, Sergey, A. , SPROUSE, Steven, T.
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1016 , G06F2212/7205 , G06F2212/7208
摘要： Systems and methods are disclosed to reduce the number of partial logical groups that are erased by writing erase patterns to memory in a non- volatile memory system. When a non-aligned erase command is received, the logical addresses of data associated with the erase command may be marked as erased. If the logical group corresponds to the size of a physical metablock, the controller may also issue a physical erase command for complete logical groups within the erase command. For those parts of the erase command that encompass only partial logical groups, the ranges of the logical block addresses marked for erasure are stored. As subsequent erase commands are received the address ranges of the erase commands are added to the previously stored address ranges. When a set of erase commands spans an entire logical group, the logical group is marked for physical erasure in its entirety.
摘要翻译：公开了系统和方法，以通过在非易失性存储器系统中将擦除模式写入存储器来减少擦除的部分逻辑组的数量。当接收到不对准的擦除命令时，可以将与擦除命令相关联的数据的逻辑地址标记为擦除。如果逻辑组对应于物理元区块的大小，则控制器还可以对擦除命令内的完整逻辑组发出物理擦除命令。对于仅包含部分逻辑组的擦除命令的那些部分，存储标记为擦除的逻辑块地址的范围。随着接下来的擦除命令被接收，擦除命令的地址范围被添加到先前存储的地址范围。当一组擦除命令跨越整个逻辑组时，逻辑组被整体标记为物理擦除。

6. 发明申请

WO2009085408A1 SYSTEM AND METHOD FOR IMPLEMENTING EXTENSIONS TO INTELLIGENTLY MANAGE RESOURCES OF A MASS STORAGE SYSTEM 审中-公开
标题翻译：实施扩展到智能管理大容量存储系统资源的系统和方法
公开(公告)号：WO2009085408A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/082957
申请日：2008-11-10
申请人： SANDISK CORPORATION , GOROBETS, Sergey, A.
发明人： GOROBETS, Sergey, A.
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/0661 , G06F3/061 , G06F3/0659 , G06F3/0679
摘要： Systems and methods for implementing extensions to intelligently manage resources of a mass storage system are disclosed. Generally, a host sends an extension of an enabled set of extensions to a mass storage system that includes at least one of command sequence information, command information or file attribute information. The host additionally sends a host application command to the mass storage system that includes logical block address information associated with the at least one of command sequence information, command information or file attribute information of the extension. Based on the received extension, the mass storage system intelligently performs operations that efficiently manage the resources of the mass storage system to reduce the frequency of operations such as data consolidation operations, data collection operations, and data copy operations, thereby increasing the data programming and reading performance of the mass storage system.
摘要翻译：公开了用于实现智能地管理大容量存储系统的资源的扩展的系统和方法。通常，主机向大容量存储系统发送启用了一组扩展的扩展，该大容量存储系统包括命令序列信息，命令信息或文件属性信息中的至少一个。主机还向大容量存储系统发送主机应用命令，该主机应用命令包括与扩展的命令序列信息，命令信息或文件属性信息中的至少一个相关联的逻辑块地址信息。基于收到的扩展，大容量存储系统智能地执行有效管理大容量存储系统的资源的操作，以减少数据合并操作，数据收集操作和数据复制操作等操作的频率，从而增加数据编程和阅读大容量存储系统的性能。

7. 发明申请

WO2009021176A9 URGENCY AND TIME WINDOW MANIPULATION TO ACCOMMODATE UNPREDICTABLE MEMORY OPERATIONS 审中-公开
标题翻译：紧急和时间窗口操作来调节不可预测的存储器操作
公开(公告)号：WO2009021176A9
公开(公告)日：2009-05-28
申请号：PCT/US2008072609
申请日：2008-08-08
申请人： SANDISK CORP , TRINGALI JAMES J , GOROBETS SERGEY A , TRAISTER SHAI , ATAKLTI YOSIEF
发明人： TRINGALI JAMES J , GOROBETS SERGEY A , TRAISTER SHAI , ATAKLTI YOSIEF
IPC分类号： G06F13/16 , G06F11/10
CPC分类号： G06F13/161 , Y02D10/14
摘要： The variable latency associated with flash memory due to background data integrity operations is managed in order to allow the flash memory to be used in isochronous systems. A system processor is notified regularly of the nature and urgency of requests for time to ensure data integrity. Minimal interruptions of system processing are achieved and operation is ensured in the event of a power interruption.
摘要翻译：管理由于背景数据完整性操作而与闪存相关联的可变延迟，以便允许在同步系统中使用闪存。系统处理器定期通知请求时间的性质和紧迫性，以确保数据的完整性。实现系统处理的最小中断，并且在电源中断的情况下确保操作。

8. 发明申请

WO2005066974A1 ADAPTIVE DETERMINISTIC GROUPING OF BLOCKS INTO MULTI-BLOCK UNITS 审中-公开
标题翻译：块的自适应确定分组到多块单元
公开(公告)号：WO2005066974A1
公开(公告)日：2005-07-21
申请号：PCT/US2004/042400
申请日：2004-12-15
申请人： SANDISK CORPORATION , GONZALEZ, Carlos, J. , BRYCE, Alan, D. , GOROBETS, Sergey, A. , BENNETT, Alan, D.
发明人： GONZALEZ, Carlos, J. , BRYCE, Alan, D. , GOROBETS, Sergey, A. , BENNETT, Alan, D.
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G06F12/0246 , G06F2212/7201 , G06F2212/7208 , G11C29/808
摘要： The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or "metablocks". After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing.
摘要翻译：本发明提出了用于将非易失性存储器的物理块链接到复合逻辑结构或“元区块”中的技术。在确定好的物理块到元区块的初始链接之后，在非易失性存储器中维护链接的记录，在需要时可以容易地访问。在一组实施例中，根据算法确定性地形成初始链接，并且可以根据存储器中的任何坏块的模式进行优化。随着额外的坏块出现，链接被更新，通过替换与优质块链接的坏块，优选地与它们所替换的块相同的存储器子阵列来更新。

9. 发明申请

WO2009021176A3 URGENCY AND TIME WINDOW MANIPULATION TO ACCOMMODATE UNPREDICTABLE MEMORY OPERATIONS 审中-公开
公开(公告)号：WO2009021176A3
公开(公告)日：2009-02-12
申请号：PCT/US2008/072609
申请日：2008-08-08
申请人： SANDISK CORPORATION , TRINGALI, James, J. , GOROBETS, Sergey, A. , TRAISTER, Shai , ATAKLTI, Yosief
发明人： TRINGALI, James, J. , GOROBETS, Sergey, A. , TRAISTER, Shai , ATAKLTI, Yosief
IPC分类号： G06F13/16 , G06F11/10
摘要： The variable latency associated with flash memory due to background data integrity operations is managed in order to allow the flash memory to be used in isochronous systems. A system processor is notified regularly of the nature and urgency of requests for time to ensure data integrity. Minimal interruptions of system processing are achieved and operation is ensured in the event of a power interruption.

10. 发明申请

WO2008156682A1 MEMORY DEVICE AND METHOD FOR WRITING DATA OF AN ATOMIC TRANSACTION 审中-公开
标题翻译：用于写入原子交易数据的存储器件和方法
公开(公告)号：WO2008156682A1
公开(公告)日：2008-12-24
申请号：PCT/US2008/007418
申请日：2008-06-13
申请人： SANDISK CORPORATION , TOMLIN, Andrew , GOROBETS, Sergey, A. , ELHAMIAS, Reuven , TRAISTER, Shai , BENNETT, Alan, D.
发明人： TOMLIN, Andrew , GOROBETS, Sergey, A. , ELHAMIAS, Reuven , TRAISTER, Shai , BENNETT, Alan, D.
IPC分类号： G06F9/46
CPC分类号： G06F9/466
摘要： A memory device and method for writing data of an atomic transaction is disclosed. In one embodiment, data of an atomic transaction is written to a first memory in a memory device. A determination is made regarding whether all of the data of the atomic transaction was written to the first memory. The data of the atomic transaction is read from the first memory and written to a second memory in the memory device only if it is determined that all of the data of the atomic transaction was written to the first memory.
摘要翻译：公开了一种用于写入原子事务的数据的存储器件和方法。在一个实施例中，将原子事务的数据写入存储器件中的第一存储器。确定原子事务的所有数据是否被写入第一存储器。仅当确定原子事务的所有数据被写入到第一存储器时，才从第一存储器读取原子事务的数据并将其写入存储器件中的第二存储器。

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