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1. 发明申请

WO2010077885A2 EXTENDING CACHE COHERENCY PROTOCOLS TO SUPPORT LOCALLY BUFFERED DATA 审中-公开
标题翻译：扩展高速缓存一致性协议以支持本地缓冲数据
公开(公告)号：WO2010077885A2
公开(公告)日：2010-07-08
申请号：PCT/US2009/068121
申请日：2009-12-15
申请人： INTEL CORPORATION , SHEAFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , COHEN, Ehud , MARGULIS, Oleg , SADE, Raanan
发明人： SHEAFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , COHEN, Ehud , MARGULIS, Oleg , SADE, Raanan
IPC分类号： G06F9/06 , G06F9/46 , G06F12/00 , G06F5/00
CPC分类号： G06F9/3834 , G06F9/467 , G06F12/0831 , G06F12/084
摘要： A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible.
摘要翻译：本文描述了用于扩展高速缓存一致性以保持缓冲数据以支持事务执行的方法和设备。引用与数据项相关联的地址的事务存储操作以缓存的方式执行。这里，与用于保存数据项的高速缓存行相关联的一致性状态被转换到缓冲状态。响应于缓存数据项的本地请求，提供数据项以确保内部事务顺序排序。但是，为了响应外部访问请求，提供未命中响应以确保事务更新的数据项在提交之前不会全局可见。提交后，缓冲行将转换为修改状态，以使数据项全局可见。

2. 发明申请

WO2010077884A2 MEMORY MODEL FOR HARDWARE ATTRIBUTES WITHIN A TRANSACTIONAL MEMORY SYSTEM 审中-公开
标题翻译：一种事务存储系统中硬件属性的存储模型
公开(公告)号：WO2010077884A2
公开(公告)日：2010-07-08
申请号：PCT/US2009/068114
申请日：2009-12-15
申请人： INTEL CORPORATION , SHEAFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , COHEN, Ehud , MARGULIS, Oleg
发明人： SHEAFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , COHEN, Ehud , MARGULIS, Oleg
IPC分类号： G06F12/08 , G06F9/06
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/3838 , G06F11/0715 , G06F11/0724 , G06F11/073 , G06F11/0751 , G06F11/3017 , G06F11/3037 , G06F11/3089 , G06F11/3471 , G06F12/0831 , G06F12/084 , G06F2201/885
摘要： A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.
摘要翻译：这里描述了一种用于提供硬件属性的存储器模型以支持事务执行的方法和设备。在遇到加载硬件属性（例如加载读取监视器，写入监视器或缓冲属性的测试监视器操作）时，响应指示硬件属性已丢失的丢失字段而发出故障。此外，基于地址依赖性和访问类型依赖性，为属性访问操作提供诸如阻塞和转发之类的依赖性动作。因此，属性丢失和测试的不同场景被允许并限制在内存模型中。

3. 发明申请

WO2010077850A3 READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS 审中-公开
公开(公告)号：WO2010077850A3
公开(公告)日：2010-07-08
申请号：PCT/US2009/068004
申请日：2009-12-15
申请人： INTEL CORPORATION , SHAEFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , SADE, Raanan , COHEN, Ehud , MARGULIS, Oleg
发明人： SHAEFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , SADE, Raanan , COHEN, Ehud , MARGULIS, Oleg
IPC分类号： G06F12/00 , G06F11/30 , G06F13/16 , G06F12/08
摘要： A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.

4. 发明申请

WO2010077842A3 METAPHYSICAL ADDRESS SPACE FOR HOLDING LOSSY METADATA IN HARDWARE 审中-公开
公开(公告)号：WO2010077842A3
公开(公告)日：2010-07-08
申请号：PCT/US2009/067983
申请日：2009-12-15
申请人： INTEL CORPORATION , SHAEFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , SADE, Raanan , COHEN, Ehud , MARGULIS, Oleg
发明人： SHAEFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , SADE, Raanan , COHEN, Ehud , MARGULIS, Oleg
IPC分类号： G06F9/06 , G06F9/46 , G06F12/00
摘要： A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.

5. 发明申请

WO2011163417A2 METHOD AND SYSTEM TO REDUCE THE POWER CONSUMPTION OF A MEMORY DEVICE 审中-公开
标题翻译：降低存储器件功耗的方法和系统
公开(公告)号：WO2011163417A2
公开(公告)日：2011-12-29
申请号：PCT/US2011/041527
申请日：2011-06-22
申请人： INTEL CORPORATION , COHEN, Ehud , MARGULIS, Oleg , SADE, Rannan , SHWARTSMAN, Stanislav
发明人： COHEN, Ehud , MARGULIS, Oleg , SADE, Rannan , SHWARTSMAN, Stanislav
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F12/0864 , G06F12/0859 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.
摘要翻译：一种降低存储器件功耗的方法和系统。在本发明的一个实施例中，存储器件是N路组合关联级（L1）高速缓冲存储器，并且存在与数据高速缓冲存储器耦合的逻辑，以便于仅访问N- 响应于加载指令或存储指令，单向设置关联L1高速缓冲存储器。通过减少针对每个加载或存储请求访问N路组合关联的L1高速缓冲存储器的方法的数量，在本发明的一个实施例中，减少了N路组合关联的L1高速缓冲存储器的功率需求。在本发明的一个实施例中，当预测到对高速缓存存储器的访问仅需要N路组关联的L1高速缓冲存储器的数据阵列时，对填充缓冲器的访问被去激活或禁用。

6. 发明申请

WO2013032788A3 A 2-D GATHER INSTRUCTION AND A 2-D CACHE 审中-公开
公开(公告)号：WO2013032788A3
公开(公告)日：2013-03-07
申请号：PCT/US2012/051748
申请日：2012-08-21
申请人： INTEL CORPORATION , GINZBURG, Boris , MARGULIS, Oleg
发明人： GINZBURG, Boris , MARGULIS, Oleg
IPC分类号： G06F9/06 , G06F9/30 , G06T1/00
摘要： A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor. The two-dimensional (2-D) cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a two-dimensional structure of the 2-D image.

7. 发明申请

WO2017112361A2 METHOD AND APPARATUS FOR RECOVERING FROM BAD STORE-TO-LOAD FORWARDING IN AN OUT-OF-ORDER PROCESSOR 审中-公开
标题翻译：用于在失序处理器中恢复坏的存储负载的方法和设备
公开(公告)号：WO2017112361A2
公开(公告)日：2017-06-29
申请号：PCT/US2016/063890
申请日：2016-11-28
申请人： INTEL CORPORATION
发明人： MEKKAT, Vineeth , MARGULIS, Oleg , AGRON, Jason M. , SCHUCHMAN, Ethan , WINKEL, Sebastian , WU, Youfeng , DANKEL, Gisle
IPC分类号： G06F9/30 , G06F9/38 , G06F11/07 , G06F11/00
CPC分类号： G06F9/30185 , G06F9/3826 , G06F9/3834 , G06F9/3838 , G06F9/3865
摘要： Embodiments of apparatus and methods for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.
摘要翻译：这里描述了用于在无序处理器中检测和从不正确的存储器依赖性推测恢复的设备和方法的实施例。例如，方法的一个实施例包括：执行第一加载指令; 检测何时第一加载指令在执行期间经历了不良的存储 - 加载转发事件; 跟踪在执行期间由第一加载指令经历的不良存储 - 加载转发事件的发生; 基于所跟踪的事件来控制所述第一加载指令中的S位的启用; 响应于第一加载指令中的启用的S位产生多个加载操作，其中所述多个加载操作的执行产生与来自所述第一加载指令的执行的结果相等的结果。

8. 发明申请

WO2018057258A1 PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTION CONVERSION MODULES FOR INSTRUCTIONS WITH COMPACT INSTRUCTION ENCODINGS 审中-公开
标题翻译：用于指令编码的指令的处理器，方法，系统和指令转换模块
公开(公告)号：WO2018057258A1
公开(公告)日：2018-03-29
申请号：PCT/US2017/049452
申请日：2017-08-30
申请人： INTEL CORPORATION
发明人： CHOU, Ching-Tsun , MARGULIS, Oleg , SONDAG, Tyler N.
IPC分类号： G06F9/30
摘要： A processor of an aspect includes a decode unit to decode a prior instruction that is to have at least a first context, and a subsequent instruction. The subsequent instruction is to be after the prior instruction in original program order. The decode unit is to use the first context of the prior instruction to determine a second context for the subsequent instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the subsequent instruction based at least in part on the second context. Other processors, methods, systems, and machine-readable medium are also disclosed.
摘要翻译：一方面的处理器包括解码单元，用于解码至少具有第一上下文的在先指令和随后的指令。后续指令将按原始程序顺序在先前指令之后。解码单元将使用先前指令的第一上下文来确定后续指令的第二上下文。处理器还包括与解码单元耦合的执行单元。执行单元至少部分基于第二上下文来执行后续指令。其他处理器，方法，系统和机器可读介质也被公开。

9. 发明申请

WO2017119973A1 BINARY TRANSLATION SUPPORT USING PROCESSOR INSTRUCTION PREFIXES 审中-公开
标题翻译：二进制翻译支持使用处理器指令前缀
公开(公告)号：WO2017119973A1
公开(公告)日：2017-07-13
申请号：PCT/US2016/065011
申请日：2016-12-05
申请人： INTEL CORPORATION
发明人： MARGULIS, Oleg , AGRON, Jason M. , SONDAG, Tyler N.
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/3016
摘要： A processing system implementing techniques for binary translation support using processor instruction prefixes is provided. In one embodiment, the processing system includes a register bank having a plurality of registers to store data for use in executing instructions and a processor core operatively coupled to the register bank. An instruction to be executed by the processor core is received. The instruction is associated with a binary translator operation to translate input instruction sequences to output instruction sequences. An opcode prefix comprising a first part and a second part is identified within the instruction. The first part of the opcode prefix references the binary translator operation to be performed by the processor core. The second part of the opcode prefix identifies an extended register of the plurality of registers to be used during the binary translator operation. The extended register preserves a source register value of the plurality of registers.
摘要翻译：提供了实现使用处理器指令前缀进行二进制翻译支持的技术的处理系统。在一个实施例中，处理系统包括具有多个寄存器的寄存器组，用于存储用于执行指令的数据以及可操作地耦合到寄存器组的处理器内核。接收处理器核心执行的指令。该指令与二进制翻译器操作相关联以将输入指令序列翻译成输出指令序列。在指令内标识包括第一部分和第二部分的操作码前缀。操作码前缀的第一部分引用由处理器内核执行的二进制翻译器操作。操作码前缀的第二部分标识在二进制翻译器操作期间要使用的多个寄存器的扩展寄存器。扩展寄存器保存多个寄存器的源寄存器值。

10. 发明公开

EP3400525A1 BINARY TRANSLATION SUPPORT USING PROCESSOR INSTRUCTION PREFIXES 审中-公开
公开(公告)号：EP3400525A1
公开(公告)日：2018-11-14
申请号：EP16884152.6
申请日：2016-12-05
申请人： INTEL Corporation
发明人： MARGULIS, Oleg , AGRON, Jason M. , SONDAG, Tyler N.
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/3016
摘要： A processing system implementing techniques for binary translation support using processor instruction prefixes is provided. In one embodiment, the processing system includes a register bank having a plurality of registers to store data for use in executing instructions and a processor core coupled to the register bank. An instruction to be executed by the processor core is received. The instruction is associated with a binary translator operation to translate input instruction sequences to output instruction sequences. An opcode prefix referencing an extended register of the plurality of registers to be used during the binary translator operation. The extended register preserves a source register value of the plurality of registers.

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