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1. 发明授权

US5926406A System and method for calculating floating point exponential values in a geometry accelerator 失效
标题翻译：用于在几何加速器中计算浮点指数值的系统和方法
公开(公告)号：US5926406A
公开(公告)日：1999-07-20
申请号：US847645
申请日：1997-04-30
申请人： S Paul Tucker , Ted Rakel
发明人： S Paul Tucker , Ted Rakel
IPC分类号： G06F7/556 , G06F7/38
CPC分类号： G06F7/556 , G06F7/483
摘要： A novel system and method computes a floating point value of an exponential expression in the form of "a.sup.x " in a geometry accelerator. In accordance with one aspect of the invention, the method includes the steps of receiving the values "a" and x of the exponential expression, where both "a" and x are represented in floating point format. As will be appreciated by those skilled in the art, the values will by supplied by software through an appropriate graphics application program interface (API). The method utilizes a mantissa value of the floating point representation of "a" to index a first value in a first look-up table, the value being an approximation for log2(a). Then, the method multiplies the looked-up value by the value of x to obtain an intermediate result. This intermediate result is then partitioned into a fractional component and an integer component, wherein the fractional component is normalized/converted to floating point format. The method then utilizes a mantissa value of the floating point representation of the fractional component of the intermediate result to index a first value in a second look-up table, the value being an approximation for 2.sup.fract, where fract is the fractional component. Thereafter, the method computing 2.sup.integer, where integer is the integer component. This step may be directly computed by the math core of the geometry accelerator, since it is an integer exponent. Finally, the method multiplies the results of steps that compute the 2.sup.fract and 2.sup.integer values to obtain a final value. This final value is a close approximation of the exponential expression a.sup.x.
摘要翻译：一种新颖的系统和方法在几何加速器中以“ax”的形式计算指数表达式的浮点值。根据本发明的一个方面，该方法包括以下步骤：接收指数表达式的值“a”和x，其中“a”和“x”以浮点格式表示。如本领域技术人员将理解的，值将由软件通过适当的图形应用程序接口（API）提供。该方法利用“a”的浮点表示的尾数值来对第一查找表中的第一值进行索引，该值是log2（a）的近似值。然后，该方法将查找值乘以x的值以获得中间结果。然后将该中间结果划分为分数分量和整数分量，其中分数分量被归一化/转换为浮点格式。然后，该方法利用中间结果的分数分量的浮点表示的尾数值来索引第二查找表中的第一值，该值是2fract的近似值，其中fract是分数分量。此后，方法计算2integer，其中integer是整数分量。该步骤可以由几何加速器的数学核心直接计算，因为它是一个整数指数。最后，该方法将计算2fract和2integer值的步骤的结果相乘以获得最终值。该最终值是指数表达式ax的近似值。

2. 发明授权

US06184902B2 Centralized branch intelligence system and method for a geometry accelerator 失效
标题翻译：集中分支智能系统和几何加速器的方法
公开(公告)号：US06184902B2
公开(公告)日：2001-02-06
申请号：US08845975
申请日：1997-04-30
申请人： Alan S. Krech, Jr. , Theodore G. Rossin , Glenn W Strunk , Michael S McGrath , Edmundo Rojas , S Paul Tucker , Jon L Ashburn , Ted Rakel
发明人： Alan S. Krech, Jr. , Theodore G. Rossin , Glenn W Strunk , Michael S McGrath , Edmundo Rojas , S Paul Tucker , Jon L Ashburn , Ted Rakel
IPC分类号： G06F1516
CPC分类号： G06F9/261 , G06T1/20
摘要： The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. Finally, a branch central intelligence mechanism controls branching between the control units by defining the next address field.
摘要翻译：本发明提供一种用于通过提供分支中央智能机构来最小化空间需求并增加用于计算机图形系统的几何加速器的速度的系统和方法。在结构上，几何加速器包括多个处理元件（例如，算术逻辑单元，乘法器，分频器，比较机构，钳位机构等）和多个控制单元（例如，变换机构，分解机构，夹子机构，蝴蝶结机构，光机构，分类机构，平面方程机构，雾化机构等），其利用处理元件对图像数据执行数据处理。根据本发明，控制单元通过微代码实现在只读存储器（ROM）中。下一个地址字段与每个微代码指令相关联，并定义ROM中要执行的下一条指令的位置。多个控制单元逻辑元件分别对应控制单元和通过定义下一个地址字段在其各自的控制单元内分支的控制指令。最后，分支中央智能机构通过定义下一个地址字段来控制控制单元之间的分支。

3. 发明授权

US06219071B1 ROM-based control unit in a geometry accelerator for a computer graphics system 有权
标题翻译：用于计算机图形系统的几何加速器中基于ROM的控制单元
公开(公告)号：US06219071B1
公开(公告)日：2001-04-17
申请号：US09209934
申请日：1998-10-06
申请人： Alan S. Krech, Jr. , Theodore G. Rossin , Edmundo Rojas , Michael S McGrath , Ted Rakel , Glenn W Strunk , Jon L Ashburn , S Paul Tucker
发明人： Alan S. Krech, Jr. , Theodore G. Rossin , Edmundo Rojas , Michael S McGrath , Ted Rakel , Glenn W Strunk , Jon L Ashburn , S Paul Tucker
IPC分类号： G06F1516
CPC分类号： G06T1/20
摘要： The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls branching between the control units by defining the next address field.
摘要翻译：本发明提供了一种用于使计算机图形系统的几何加速器中的空间需求最小化并提高速度的系统和方法。在架构中，系统实现如下。几何加速器包括多个处理元件（例如，算术逻辑单元，乘法器，分频器，比较机构，钳位机构等）和多个控制单元（例如，变换机构，分解机构，夹子机构，蝴蝶结机构，光机构，分类机构，平面方程机构，雾化机构等），其利用处理元件对图像数据进行数据处理。根据本发明，控制单元通过微代码实现在只读存储器（ROM）中。下一个地址字段与每个微代码指令相关联，并定义ROM中要执行的下一条指令的位置。多个控制单元逻辑元件分别对应控制单元和通过定义下一个地址字段在其各自的控制单元内分支的控制指令。分支中央智能机构通过定义下一个地址字段来控制控制单元之间的分支。

4. 发明授权

US5956047A ROM-based control units in a geometry accelerator for a computer graphics system 失效
标题翻译：用于计算机图形系统的几何加速器中基于ROM的控制单元
公开(公告)号：US5956047A
公开(公告)日：1999-09-21
申请号：US846363
申请日：1997-04-30
申请人： Alan S. Krech, Jr. , Theodore G. Rossin , Edmundo Rojas , Michael S McGrath , Ted Rakel , Glenn W Strunk , Jon L Ashburn , S Paul Tucker
发明人： Alan S. Krech, Jr. , Theodore G. Rossin , Edmundo Rojas , Michael S McGrath , Ted Rakel , Glenn W Strunk , Jon L Ashburn , S Paul Tucker
IPC分类号： G06F9/26 , G06T1/20 , G06T11/00 , G06F15/16
CPC分类号： G06T1/20
摘要： The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls branching between the control units by defining the next address field.
摘要翻译：本发明提供了一种用于使计算机图形系统的几何加速器中的空间要求最小化并提高速度的系统和方法。在架构中，系统实现如下。几何加速器包括多个处理元件（例如，算术逻辑单元，乘法器，分频器，比较机构，钳位机构等）和多个控制单元（例如，变换机构，分解机构，夹子机构，蝴蝶结机构，光机构，分类机构，平面方程机构，雾化机构等），其利用处理元件对图像数据进行数据处理。根据本发明，控制单元通过微代码实现在只读存储器（ROM）中。下一个地址字段与每个微代码指令相关联，并定义ROM中要执行的下一条指令的位置。多个控制单元逻辑元件分别对应控制单元和通过定义下一个地址字段在其各自的控制单元内分支的控制指令。分支中央智能机构通过定义下一个地址字段来控制控制单元之间的分支。

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