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1. 发明申请

US20200026598A1 TWO DIE SYSTEM ON CHIP (SOC) FOR PROVIDING HARDWARE FAULT TOLERANCE (HFT) FOR A PAIRED SOC 审中-公开
公开(公告)号：US20200026598A1
公开(公告)日：2020-01-23
申请号：US16585104
申请日：2019-09-27
申请人： Gabriele Boschi , Gabriele Paoloni , Roger May , Nabajit Deka , Matteo Salardi
发明人： Gabriele Boschi , Gabriele Paoloni , Roger May , Nabajit Deka , Matteo Salardi
IPC分类号： G06F11/07 , G06F11/20
摘要： Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.

2. 发明申请

US20130226641A1 MONITORING PROJECT PLANS INTEGRATED WITH USER DATA STORES AND PROVIDING REWARDS 审中-公开
标题翻译：监控与用户数据存储和提供奖励的项目计划
公开(公告)号：US20130226641A1
公开(公告)日：2013-08-29
申请号：US13403999
申请日：2012-02-24
申请人： Susan Chory , Kenneth Blaine Wolfe , Steven Roger May , Mario Chenier , Michael Paul Isbell
发明人： Susan Chory , Kenneth Blaine Wolfe , Steven Roger May , Mario Chenier , Michael Paul Isbell
IPC分类号： G06Q10/06 , G06Q30/02
CPC分类号： G06Q10/0631 , G06Q10/0639 , G06Q30/0207
摘要： Embodiments enable the monitoring of project plans and the selection and application of rewards to motivate users. Project plans having one or more project content items are created according to a pre-defined schema. The project plans are integrated with user data stores, such as calendar appointments, tasks, and shopping lists. Progress indicators reflecting a completion status of the project plans are calculated for the project plans. Rewards are selected based on the progress indicators and on user preferences (e.g., collected user activity data). The rewards correspond to milestones associated with the project plans, and are integrated into the user data stores when the user reaches the corresponding milestones.
摘要翻译：实施方式可以监控项目计划，选择和应用奖励来激励用户。具有一个或多个项目内容项目的项目计划根据预定义的模式创建。项目计划与用户数据存储集成，如日历约会，任务和购物清单。对项目计划进行的反映项目计划完成情况的进度指标进行了计算。奖励是根据进度指标和用户偏好（例如收集的用户活动数据）来选择的。奖励对应于与项目计划相关的里程碑，并在用户达到相应的里程碑时被集成到用户数据存储中。

3. 发明授权

US07340596B1 Embedded processor with watchdog timer for programmable logic 有权
公开(公告)号：US07340596B1
公开(公告)日：2008-03-04
申请号：US09880734
申请日：2001-06-12
申请人： Andrew Crosland , Roger May , Edward Flaherty , Andrew Draper
发明人： Andrew Crosland , Roger May , Edward Flaherty , Andrew Draper
IPC分类号： G06F1/24
CPC分类号： G06F1/24 , Y02T10/82
摘要： A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

4. 发明授权

US07081773B1 Updating configuration for programmable logic device 失效
标题翻译：更新可编程逻辑器件的配置
公开(公告)号：US07081773B1
公开(公告)日：2006-07-25
申请号：US10886914
申请日：2004-07-07
申请人： Roger May , James Tyson , Mark Dickinson
发明人： Roger May , James Tyson , Mark Dickinson
IPC分类号： H03K19/173
CPC分类号： H03K19/17776 , H03K19/17752 , H03K19/1776
摘要： A programmable logic device is reconfigurable between two functionalities, while it is in use. The programmable logic device has a first store, into which configuration data may be downloaded from an external memory device, and a second store, in which a copy of the configuration data is maintained, with the functionality of the programmable logic device being determined by the copy of the configuration data, thereby allowing additional configuration data to be downloaded from the external memory device into the first store, while maintaining the functionality of the device. This allows the device to be used to provide two different functionalities, and to be switched between these two functionalities with minimal delay for reconfiguration of the device.
摘要翻译：可编程逻辑器件可在两个功能之间进行重新配置，同时它正在使用中。可编程逻辑器件具有可从外部存储器件下载配置数据的第一存储器和维持配置数据的副本的第二存储器，其中可编程逻辑器件的功能由配置数据的副本，从而允许在维护设备的功能的同时将附加配置数据从外部存储设备下载到第一存储器中。这允许该设备用于提供两种不同的功能，并且以最小的延迟在这两个功能之间切换以重新配置设备。

5. 发明授权

US06803785B1 I/O circuitry shared between processor and programmable logic portions of an integrated circuit 有权
标题翻译：在集成电路的处理器和可编程逻辑部分之间共享的I / O电路
公开(公告)号：US06803785B1
公开(公告)日：2004-10-12
申请号：US09880458
申请日：2001-06-12
申请人： Roger May , Igor Kostarnov , Edward H. Flaherty , Mark Dickinson
发明人： Roger May , Igor Kostarnov , Edward H. Flaherty , Mark Dickinson
IPC分类号： H03K190177
CPC分类号： G06F15/7867
摘要： The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.
摘要翻译：本发明提供了用于在芯片的可编程逻辑部分和嵌入式处理器部分之间共享I / O引脚的电路和方法。可编程逻辑部分和嵌入式处理器部分中的电路可以访问数据信号并将数据信号发送到相同的I / O引脚。数据信号被复用以控制对共享I / O引脚的访问。多路复用器可以由控制信号控制，该控制信号确定特定的I / O引脚何时由可编程逻辑部分和嵌入式处理器部分访问。将相关的I / O引脚电路配置为正确I / O标准的控制信号也由本发明的共享I / O电路复用。在发送到嵌入式处理器部分的共享I / O引脚处接收到的信号可以被同时发送到可编程逻辑部分内的监听电路。

6. 发明授权

US09082199B1 Video processing architecture 有权
标题翻译：视频处理架构
公开(公告)号：US09082199B1
公开(公告)日：2015-07-14
申请号：US11440502
申请日：2006-05-24
申请人： Andrew Crosland , Roger May
发明人： Andrew Crosland , Roger May
IPC分类号： G06T3/40 , H04N5/343
CPC分类号： G06T3/40 , H04N5/343 , H04N21/23406 , H04N21/234363 , H04N21/23805
摘要： A video processing device has an input for receiving video data, at least one processing circuit, for generating processed video data from the received video data, and a memory, for receiving the processed video data. An output circuit reads the processed video data from the memory, and generates frames of data including at least the processed video data. In order to be able to operate with an output clock frequency that may differ from the ideal output clock frequency, it is possible to vary the frame size, that is, the number of pixels of data in a frame. If an amount of processed video data stored in the memory exceeds an upper threshold, then the frame size can be reduced by reducing the number of pixels of blanking data in the output frame, thereby increasing the rate at which data is read from the memory. Conversely, if an amount of processed video data stored in the memory is lower than a lower threshold, then the frame size can be increased by increasing the number of pixels of blanking data in the output frame, thereby reducing the rate at which data is read from the memory.
摘要翻译：视频处理装置具有用于接收视频数据的输入，用于从所接收的视频数据产生经处理的视频数据的至少一个处理电路和用于接收经处理的视频数据的存储器。输出电路从存储器读取经处理的视频数据，并产生至少包括经处理的视频数据的数据帧。为了能够以可能与理想输出时钟频率不同的输出时钟频率进行操作，可以改变帧大小，即，帧中数据的像素数量。如果存储在存储器中的经处理的视频数据量超过上阈值，则可以通过减少输出帧中的消隐数据的像素数来减小帧大小，从而增加从存储器读取数据的速率。相反，如果存储在存储器中的已处理视频数据量低于下限阈值，则可以通过增加输出帧中的消隐数据的像素数来增加帧大小，从而降低读取数据的速率从记忆。

7. 发明授权

US08190828B1 Embedded processor with dual-port SRAM for programmable logic 有权
标题翻译：具有双端口SRAM的嵌入式处理器，用于可编程逻辑
公开(公告)号：US08190828B1
公开(公告)日：2012-05-29
申请号：US12465525
申请日：2009-05-13
申请人： Roger May , Andrew Draper , Paul Metzgen , Neil Thorne
发明人： Roger May , Andrew Draper , Paul Metzgen , Neil Thorne
IPC分类号： G06F12/00
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port. When the second port is accessing the first plurality of memory cells, the arbiter prevents the first port from accessing the first plurality of memory cells, and when the second port is accessing the first plurality of memory cells, the arbiter allows the first port to access the second plurality of memory cells.
摘要翻译：包括具有双端口SRAM的嵌入式处理器的可编程逻辑器件的方法和装置。可编程逻辑集成电路包括具有多个逻辑元件的可编程逻辑部分，可编程地可配置为实现用户定义的组合或注册的逻辑功能，以及耦合到可编程逻辑部分的嵌入式处理器部分。嵌入式处理器部分包括处理器和耦合到处理器的存储器块。存储器块包括用于存储数据的第一多个存储器单元，用于存储数据的第二多个存储器单元，耦合到第一和第二多个存储器单元的第一端口，耦合到第一和第二多个存储器的第二端口小区和耦合到第一端口和第二端口的仲裁器。当第二端口正在访问第一多个存储器单元时，仲裁器防止第一端口访问第一多个存储单元，并且当第二端口正在访问第一多个存储单元时，仲裁器允许第一端口访问第二组多个存储单元。

8. 发明授权

US07917706B1 SDRAM controller 有权
标题翻译： SDRAM控制器
公开(公告)号：US07917706B1
公开(公告)日：2011-03-29
申请号：US10737645
申请日：2003-12-15
申请人： Roger May
发明人： Roger May
IPC分类号： G06F13/00 , G06F13/36
CPC分类号： G06F13/1642
摘要： A SDRAM controller prioritizes memory access requests to maximize efficient use of the bandwidth of the memory data bus, and also gives different priorities to access requests received on its different inputs. The SDRAM controller has multiple inputs, at least one of which allows connections to multiple bus master devices. The SDRAM controller forms a queue of bus access requests, based amongst other things on a relative priority given to the input on which a request is received. When a request is received on an input which allows connections to multiple bus master devices, the SDRAM controller forms the queue of bus access requests, based amongst other things on a relative priority given to the bus master device which made the request.
摘要翻译： SDRAM控制器优先考虑存储器访问请求，以最大限度地有效利用存储器数据总线的带宽，并且还给出访问在其不同输入上接收的请求的不同优先级。 SDRAM控制器具有多个输入，其中至少一个允许连接到多个总线主设备。除了其他事项之外，SDRAM控制器形成总线访问请求的队列，这是基于接收到请求的输入的相对优先级。当允许连接到多个总线主设备的输入上接收到请求时，SDRAM控制器基于提供请求的总线主设备的相对优先级，形成总线访问请求的队列。

9. 发明授权

US07546424B1 Embedded processor with dual-port SRAM for programmable logic 有权
标题翻译：具有双端口SRAM的嵌入式处理器，用于可编程逻辑
公开(公告)号：US07546424B1
公开(公告)日：2009-06-09
申请号：US11445703
申请日：2006-06-02
申请人： Roger May , Andrew Draper , Paul Metzgen , Neil Thorne
发明人： Roger May , Andrew Draper , Paul Metzgen , Neil Thorne
IPC分类号： G06F12/00
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port. When the second port is accessing the first plurality of memory cells, the arbiter prevents the first port from accessing the first plurality of memory cells, and when the second port is accessing the first plurality of memory cells, the arbiter allows the first port to access the second plurality of memory cells.
摘要翻译：包括具有双端口SRAM的嵌入式处理器的可编程逻辑器件的方法和装置。可编程逻辑集成电路包括具有多个逻辑元件的可编程逻辑部分，可编程地可配置为实现用户定义的组合或注册的逻辑功能，以及耦合到可编程逻辑部分的嵌入式处理器部分。嵌入式处理器部分包括处理器和耦合到处理器的存储器块。存储器块包括用于存储数据的第一多个存储器单元，用于存储数据的第二多个存储器单元，耦合到第一和第二多个存储器单元的第一端口，耦合到第一和第二多个存储器的第二端口小区和耦合到第一端口和第二端口的仲裁器。当第二端口正在访问第一多个存储器单元时，仲裁器防止第一端口访问第一多个存储单元，并且当第二端口正在访问第一多个存储单元时，仲裁器允许第一端口访问第二组多个存储单元。

10. 发明授权

US07446561B2 I/O circuitry shared between processor and programmable logic portions of an integrated circuit 有权
标题翻译：在集成电路的处理器和可编程逻辑部分之间共享的I / O电路
公开(公告)号：US07446561B2
公开(公告)日：2008-11-04
申请号：US11283402
申请日：2005-11-17
申请人： Roger May , Igor Kostarnov , Edward H Flaherty , Mark Dickinson
发明人： Roger May , Igor Kostarnov , Edward H Flaherty , Mark Dickinson
IPC分类号： H03K19/177
CPC分类号： G06F15/7867
摘要： The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.
摘要翻译：本发明提供了用于在芯片的可编程逻辑部分和嵌入式处理器部分之间共享I / O引脚的电路和方法。可编程逻辑部分和嵌入式处理器部分中的电路可以访问数据信号并将数据信号发送到相同的I / O引脚。数据信号被复用以控制对共享I / O引脚的访问。多路复用器可以由控制信号控制，该控制信号确定特定的I / O引脚何时由可编程逻辑部分和嵌入式处理器部分访问。将相关的I / O引脚电路配置为正确I / O标准的控制信号也由本发明的共享I / O电路复用。在发送到嵌入式处理器部分的共享I / O引脚处接收到的信号可以被同时发送到可编程逻辑部分内的监听电路。

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