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1. 发明授权

US08190828B1 Embedded processor with dual-port SRAM for programmable logic 有权
标题翻译：具有双端口SRAM的嵌入式处理器，用于可编程逻辑
公开(公告)号：US08190828B1
公开(公告)日：2012-05-29
申请号：US12465525
申请日：2009-05-13
申请人： Roger May , Andrew Draper , Paul Metzgen , Neil Thorne
发明人： Roger May , Andrew Draper , Paul Metzgen , Neil Thorne
IPC分类号： G06F12/00
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port. When the second port is accessing the first plurality of memory cells, the arbiter prevents the first port from accessing the first plurality of memory cells, and when the second port is accessing the first plurality of memory cells, the arbiter allows the first port to access the second plurality of memory cells.
摘要翻译：包括具有双端口SRAM的嵌入式处理器的可编程逻辑器件的方法和装置。可编程逻辑集成电路包括具有多个逻辑元件的可编程逻辑部分，可编程地可配置为实现用户定义的组合或注册的逻辑功能，以及耦合到可编程逻辑部分的嵌入式处理器部分。嵌入式处理器部分包括处理器和耦合到处理器的存储器块。存储器块包括用于存储数据的第一多个存储器单元，用于存储数据的第二多个存储器单元，耦合到第一和第二多个存储器单元的第一端口，耦合到第一和第二多个存储器的第二端口小区和耦合到第一端口和第二端口的仲裁器。当第二端口正在访问第一多个存储器单元时，仲裁器防止第一端口访问第一多个存储单元，并且当第二端口正在访问第一多个存储单元时，仲裁器允许第一端口访问第二组多个存储单元。

2. 发明授权

US07546424B1 Embedded processor with dual-port SRAM for programmable logic 有权
标题翻译：具有双端口SRAM的嵌入式处理器，用于可编程逻辑
公开(公告)号：US07546424B1
公开(公告)日：2009-06-09
申请号：US11445703
申请日：2006-06-02
申请人： Roger May , Andrew Draper , Paul Metzgen , Neil Thorne
发明人： Roger May , Andrew Draper , Paul Metzgen , Neil Thorne
IPC分类号： G06F12/00
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port. When the second port is accessing the first plurality of memory cells, the arbiter prevents the first port from accessing the first plurality of memory cells, and when the second port is accessing the first plurality of memory cells, the arbiter allows the first port to access the second plurality of memory cells.
摘要翻译：包括具有双端口SRAM的嵌入式处理器的可编程逻辑器件的方法和装置。可编程逻辑集成电路包括具有多个逻辑元件的可编程逻辑部分，可编程地可配置为实现用户定义的组合或注册的逻辑功能，以及耦合到可编程逻辑部分的嵌入式处理器部分。嵌入式处理器部分包括处理器和耦合到处理器的存储器块。存储器块包括用于存储数据的第一多个存储器单元，用于存储数据的第二多个存储器单元，耦合到第一和第二多个存储器单元的第一端口，耦合到第一和第二多个存储器的第二端口小区和耦合到第一端口和第二端口的仲裁器。当第二端口正在访问第一多个存储器单元时，仲裁器防止第一端口访问第一多个存储单元，并且当第二端口正在访问第一多个存储单元时，仲裁器允许第一端口访问第二组多个存储单元。

3. 发明授权

US07096324B1 Embedded processor with dual-port SRAM for programmable logic 有权
公开(公告)号：US07096324B1
公开(公告)日：2006-08-22
申请号：US09881226
申请日：2001-06-12
申请人： Roger May , Andrew Draper , Paul Metzgen , Neil Thorne
发明人： Roger May , Andrew Draper , Paul Metzgen , Neil Thorne
IPC分类号： G06F12/02
CPC分类号： G06F17/5045 , G06F17/5068
摘要： Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port. When the second port is accessing the first plurality of memory cells, the arbiter prevents the first port from accessing the first plurality of memory cells, and when the second port is accessing the first plurality of memory cells, the arbiter allows the first port to access the second plurality of memory cells.

4. 发明授权

US08930922B2 Software-to-hardware compiler with symbol set inference analysis 有权
标题翻译：具有符号集推理分析的软件到硬件编译器
公开(公告)号：US08930922B2
公开(公告)日：2015-01-06
申请号：US13613581
申请日：2012-09-13
申请人： Paul Metzgen
发明人： Paul Metzgen
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5054
摘要： A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources.
摘要翻译：提供了一种在可编程逻辑资源中生成硬件结构的软件到硬件编译器。可编程逻辑资源可以被优化为被配置为在除可编程逻辑资源（例如，RAM）之外的存储器设备上进行区域的附加拷贝。这有助于在单个时钟周期内进行多次读取。符号集分析用于最小化区域的大小以允许更有效地使用硬件资源。

5. 发明授权

US07523421B1 Method and apparatus for reducing the cost of multiplexer circuitry 有权
标题翻译：降低多路复用器电路成本的方法和装置
公开(公告)号：US07523421B1
公开(公告)日：2009-04-21
申请号：US11317096
申请日：2005-12-22
申请人： Dominic J Nancekievill , Paul Metzgen
发明人： Dominic J Nancekievill , Paul Metzgen
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Methods and apparatus are provided for reducing the cost of multiplexer circuitry. Electrically equivalent data inputs and corresponding multiplexers can be eliminated from a multiplexer cone. A new multiplexer and new selection circuitry can be added to preserve the logical function of the cone. Such a method can result in substantial cost savings in the multiplexer circuitry, especially when applied to a multiplexer cone bus of relatively large width.
摘要翻译：提供了用于降低多路复用器电路的成本的方法和装置。电子等效数据输入和相应的多路复用器可以从多路复用器锥中消除。可以添加新的多路复用器和新的选择电路，以保持锥的逻辑功能。这种方法可以导致多路复用器电路中的大量成本节省，特别是当应用于相对较大宽度的多路复用器锥形总线时。

6. 发明授权

US07441105B1 Reducing multiplexer circuitry for operand select logic associated with a processor 有权
标题翻译：减少与处理器相关联的操作数选择逻辑的多路复用器电路
公开(公告)号：US07441105B1
公开(公告)日：2008-10-21
申请号：US10870749
申请日：2004-06-16
申请人： Paul Metzgen
发明人： Paul Metzgen
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3001 , G06F7/5443 , G06F7/57 , G06F9/3012
摘要： Methods and apparatus are provided for reducing the amount of resources allocated for handling multiplexing in a processor. Characteristics associated with processing blocks are analyzed. Operand restrictions and register groups can be configured to allow the use of more resource efficient multiplexing circuitry in a processor.
摘要翻译：提供了用于减少在处理器中分配用于处理复用的资源量的方法和装置。分析与处理块相关的特征。操作数限制和寄存器组可以配置为允许在处理器中使用更多资源有效的复用电路。

7. 发明申请

US20050187999A1 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US20050187999A1
公开(公告)日：2005-08-25
申请号：US10783829
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/499 , G06F7/52 , G06F7/523 , G06F7/544
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在MAC块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

8. 发明授权

US08332831B1 Software-to-hardware compiler with symbol set inference analysis 有权
标题翻译：具有符号集推理分析的软件到硬件编译器
公开(公告)号：US08332831B1
公开(公告)日：2012-12-11
申请号：US12023880
申请日：2008-01-31
申请人： Paul Metzgen
发明人： Paul Metzgen
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5054
摘要： A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources.
摘要翻译：提供了一种在可编程逻辑资源中生成硬件结构的软件到硬件编译器。可编程逻辑资源可以被优化为被配置为在除可编程逻辑资源（例如，RAM）之外的存储器设备上进行区域的附加拷贝。这有助于在单个时钟周期内进行多次读取。符号集分析用于最小化区域的大小以允许更有效地使用硬件资源。

9. 发明授权

US07475221B1 Circular buffer addressing 有权
标题翻译：循环缓冲区寻址
公开(公告)号：US07475221B1
公开(公告)日：2009-01-06
申请号：US10893655
申请日：2004-07-16
申请人： Paul Metzgen , Dominic Nancekievill , Tracy Miranda
发明人： Paul Metzgen , Dominic Nancekievill , Tracy Miranda
IPC分类号： G06F12/00
CPC分类号： G06F5/10
摘要： Methods and apparatus are provided for performing circular buffer addressing. Upper boundaries, lower boundaries, circular buffer lengths, addresses, and offsets are set to allow circular buffer access efficiency. An addition/subtraction unit is provided to simplify implementation. Comparators are rearranged and in some instances replaced with combined adder/comparator logic units. The additional logic units and the rearrangement allow efficient implementation of circular buffer addressing, particularly on programmable chips.
摘要翻译：提供了用于执行循环缓冲器寻址的方法和装置。上边界，下边界，循环缓冲区长度，地址和偏移被设置为允许循环缓冲区访问效率。提供加减法单元以简化实现。比较器被重新排列，并且在某些情况下被组合的加法器/比较器逻辑单元替代。附加逻辑单元和重新布置允许循环缓冲器寻址的有效实现，特别是在可编程芯片上。

10. 发明授权

US07437401B2 Multiplier-accumulator block mode splitting 有权
标题翻译：乘法器 - 累加器块模式分割
公开(公告)号：US07437401B2
公开(公告)日：2008-10-14
申请号：US10783820
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
IPC分类号： G06F7/48
CPC分类号： G06F7/5443 , H03K19/17732
摘要： A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.
摘要翻译：提供了一种可编程逻辑器件，其包括具有模式分离能力的MAC块。可以同时实现不同的操作模式，从而可以在不同的操作模式之间分配MAC块的乘法器和其它DSP电路。例如，可以使用一个乘法器来实现乘法模式，而另外两个乘法器可以用于实现两个乘法器模式的和。

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