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1. 发明授权

US07340596B1 Embedded processor with watchdog timer for programmable logic 有权
公开(公告)号：US07340596B1
公开(公告)日：2008-03-04
申请号：US09880734
申请日：2001-06-12
申请人： Andrew Crosland , Roger May , Edward Flaherty , Andrew Draper
发明人： Andrew Crosland , Roger May , Edward Flaherty , Andrew Draper
IPC分类号： G06F1/24
CPC分类号： G06F1/24 , Y02T10/82
摘要： A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

2. 发明授权

US07350178B1 Embedded processor with watchdog timer for programmable logic 有权
标题翻译：具有可编程逻辑的看门狗定时器的嵌入式处理器
公开(公告)号：US07350178B1
公开(公告)日：2008-03-25
申请号：US10711137
申请日：2004-08-27
申请人： Andrew Crosland , Roger May , Edward Flaherty , Andrew Draper
发明人： Andrew Crosland , Roger May , Edward Flaherty , Andrew Draper
IPC分类号： G06F17/50
CPC分类号： G06F1/24 , Y02T10/82
摘要： A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.
摘要翻译：可编程逻辑集成电路具有带看门狗定时器电路的嵌入式处理器。看门狗定时器电路用于检测软件或硬件故障。在一个实现中，看门狗定时器电路包括一个计数器寄存器，它使每个时钟前进（例如递增或递减）。为了防止看门狗定时器电路触发，看门狗定时器电路应由软件复位或重新加载。例如，计数寄存器可能被重置为一个值来开始计数。如果计数寄存器被允许计数到最终值或最大值，则看门狗定时器电路将被触发，产生使可编程逻辑集成电路复位的触发信号。复位导致重新加载用于对集成数据的可编程逻辑和嵌入式处理器部分进行编程的配置数据。配置数据可以存储在外部非易失性存储器中。

3. 发明授权

US07064578B1 Distributed bus structure 失效
标题翻译：分布式总线结构
公开(公告)号：US07064578B1
公开(公告)日：2006-06-20
申请号：US10751283
申请日：2003-12-30
申请人： Andrew Crosland , Roger May , Stephane Caneau , Andrew Draper , Edward Flaherty
发明人： Andrew Crosland , Roger May , Stephane Caneau , Andrew Draper , Edward Flaherty
IPC分类号： H03K19/173
CPC分类号： H03K19/17736
摘要： A programmable logic device includes a routing structure, which takes the form of multiple distributed OR gates, which are positioned within the device to allow signals to be input from spaced apart logic elements, and present the input signals to other logic elements, which, again, may be spaced apart throughout the device. Each of the distributed OR gates, and its connections to the other logic elements, acts as a multiplexer. Sufficient of these distributed OR gates are provided to allow a bus structure to be implemented within the device. Since the OR gates are provided separately from the logic elements of the programmable logic device, the required bus structure can be implemented more efficiently.
摘要翻译：可编程逻辑器件包括路由结构，其采用多个分布式或门的形式，其位于该器件内，以允许从间隔开的逻辑元件输入信号，并将输入信号呈现给其它逻辑元件，这再次，可以在整个装置中间隔开。每个分配的OR门及其与其他逻辑元件的连接充当多路复用器。提供足够的这些分配的或门以允许总线结构在设备内实现。由于或门与可编程逻辑器件的逻辑元件分开提供，所以可以更有效地实现所需的总线结构。

4. 发明授权

US07026840B1 Programmable logic device 失效
标题翻译：可编程逻辑器件
公开(公告)号：US07026840B1
公开(公告)日：2006-04-11
申请号：US10792042
申请日：2004-03-02
申请人： Roger May , Andrew Crosland , Edward Flaherty
发明人： Roger May , Andrew Crosland , Edward Flaherty
IPC分类号： H03K19/177
CPC分类号： H03K19/17772 , H03K19/17732 , H03K19/17784
摘要： A programmable logic device is provided with multiple power supplies such that, in one mode of operation, power can be disconnected from at least one part of the programmable logic device, while maintaining power at least to an interface component of the programmable logic device, or to a memory component in which current configuration data are stored, thereby avoiding the need for a configuration sequence when power is reapplied to the whole device. The programmable logic device may be provided as an integrated circuit, having multiple pairs of pins for connection to a supply voltage. Each of the pairs of pins provides power for a different subsection of the programmable logic device.
摘要翻译：可编程逻辑器件设置有多个电源，使得在一种操作模式中，可以将功率与可编程逻辑器件的至少一部分断开，同时至少保持至可编程逻辑器件的接口部件的功率，或到存储当前配置数据的存储器组件，从而避免了当将电力重新应用于整个设备时对配置顺序的需要。可编程逻辑器件可以被提供为集成电路，具有用于连接到电源电压的多对引脚。每对引脚为可编程逻辑器件的不同子部分提供电源。

5. 发明授权

US06937061B1 Address decoder for programmable logic device 有权
标题翻译：可编程逻辑器件的地址解码器
公开(公告)号：US06937061B1
公开(公告)日：2005-08-30
申请号：US10751229
申请日：2003-12-30
申请人： Andrew Crosland , Roger May , Stephane Cauneau , Andrew Draper , Edward Flaherty
发明人： Andrew Crosland , Roger May , Stephane Cauneau , Andrew Draper , Edward Flaherty
IPC分类号： G06F9/38 , G06F12/06 , H03K19/173
CPC分类号： G06F12/0661 , G06F9/3879 , G06F12/06
摘要： A programmable logic device includes a gate array formed from programmable logic elements, and at least one address decoder structure. The address decoder has a first stage, for receiving bits of an address, and for masking out a first group of least significant bits of said address; a second stage, for comparing a second group of most significant bits of said address with respective comparison bits; and a third stage, for providing an output when all of the bits in said second group of bits of said address match their respective comparison bits. Thus, the address decoder can determine when a received address falls within a range of addresses associated with the address decoder. Multiple address decoders may be provided at spaced apart locations within the gate array, and one address decoder can be associated with each slave device implemented in the gate array. The programmable logic device may be used to implement a bus structure, with a bus master which may be in the form of an embedded processor. One of the multiple address decoders can then be associated with each slave device in the bus structure.
摘要翻译：可编程逻辑器件包括由可编程逻辑元件形成的门阵列和至少一个地址解码器结构。地址解码器具有第一级，用于接收地址的位，并且用于掩蔽所述地址的第一组最低有效位; 第二级，用于将所述地址的第二组最高有效位与相应的比较位进行比较; 以及第三级，用于当所述地址的所述第二组位中的所有位与其各自的比较位相匹配时提供输出。因此，地址解码器可以确定接收到的地址何时落在与地址解码器相关联的地址的范围内。可以在门阵列内的间隔开的位置处提供多个地址解码器，并且一个地址解码器可以与在门阵列中实现的每个从设备相关联。可编程逻辑器件可用于实现总线结构，总线主机可以是嵌入式处理器的形式。多个地址解码器中的一个可以与总线结构中的每个从设备相关联。

6. 发明授权

US09082199B1 Video processing architecture 有权
标题翻译：视频处理架构
公开(公告)号：US09082199B1
公开(公告)日：2015-07-14
申请号：US11440502
申请日：2006-05-24
申请人： Andrew Crosland , Roger May
发明人： Andrew Crosland , Roger May
IPC分类号： G06T3/40 , H04N5/343
CPC分类号： G06T3/40 , H04N5/343 , H04N21/23406 , H04N21/234363 , H04N21/23805
摘要： A video processing device has an input for receiving video data, at least one processing circuit, for generating processed video data from the received video data, and a memory, for receiving the processed video data. An output circuit reads the processed video data from the memory, and generates frames of data including at least the processed video data. In order to be able to operate with an output clock frequency that may differ from the ideal output clock frequency, it is possible to vary the frame size, that is, the number of pixels of data in a frame. If an amount of processed video data stored in the memory exceeds an upper threshold, then the frame size can be reduced by reducing the number of pixels of blanking data in the output frame, thereby increasing the rate at which data is read from the memory. Conversely, if an amount of processed video data stored in the memory is lower than a lower threshold, then the frame size can be increased by increasing the number of pixels of blanking data in the output frame, thereby reducing the rate at which data is read from the memory.
摘要翻译：视频处理装置具有用于接收视频数据的输入，用于从所接收的视频数据产生经处理的视频数据的至少一个处理电路和用于接收经处理的视频数据的存储器。输出电路从存储器读取经处理的视频数据，并产生至少包括经处理的视频数据的数据帧。为了能够以可能与理想输出时钟频率不同的输出时钟频率进行操作，可以改变帧大小，即，帧中数据的像素数量。如果存储在存储器中的经处理的视频数据量超过上阈值，则可以通过减少输出帧中的消隐数据的像素数来减小帧大小，从而增加从存储器读取数据的速率。相反，如果存储在存储器中的已处理视频数据量低于下限阈值，则可以通过增加输出帧中的消隐数据的像素数来增加帧大小，从而降低读取数据的速率从记忆。

7. 发明申请

US20200026598A1 TWO DIE SYSTEM ON CHIP (SOC) FOR PROVIDING HARDWARE FAULT TOLERANCE (HFT) FOR A PAIRED SOC 审中-公开
公开(公告)号：US20200026598A1
公开(公告)日：2020-01-23
申请号：US16585104
申请日：2019-09-27
申请人： Gabriele Boschi , Gabriele Paoloni , Roger May , Nabajit Deka , Matteo Salardi
发明人： Gabriele Boschi , Gabriele Paoloni , Roger May , Nabajit Deka , Matteo Salardi
IPC分类号： G06F11/07 , G06F11/20
摘要： Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.

8. 发明授权

US07081773B1 Updating configuration for programmable logic device 失效
标题翻译：更新可编程逻辑器件的配置
公开(公告)号：US07081773B1
公开(公告)日：2006-07-25
申请号：US10886914
申请日：2004-07-07
申请人： Roger May , James Tyson , Mark Dickinson
发明人： Roger May , James Tyson , Mark Dickinson
IPC分类号： H03K19/173
CPC分类号： H03K19/17776 , H03K19/17752 , H03K19/1776
摘要： A programmable logic device is reconfigurable between two functionalities, while it is in use. The programmable logic device has a first store, into which configuration data may be downloaded from an external memory device, and a second store, in which a copy of the configuration data is maintained, with the functionality of the programmable logic device being determined by the copy of the configuration data, thereby allowing additional configuration data to be downloaded from the external memory device into the first store, while maintaining the functionality of the device. This allows the device to be used to provide two different functionalities, and to be switched between these two functionalities with minimal delay for reconfiguration of the device.
摘要翻译：可编程逻辑器件可在两个功能之间进行重新配置，同时它正在使用中。可编程逻辑器件具有可从外部存储器件下载配置数据的第一存储器和维持配置数据的副本的第二存储器，其中可编程逻辑器件的功能由配置数据的副本，从而允许在维护设备的功能的同时将附加配置数据从外部存储设备下载到第一存储器中。这允许该设备用于提供两种不同的功能，并且以最小的延迟在这两个功能之间切换以重新配置设备。

9. 发明授权

US06803785B1 I/O circuitry shared between processor and programmable logic portions of an integrated circuit 有权
标题翻译：在集成电路的处理器和可编程逻辑部分之间共享的I / O电路
公开(公告)号：US06803785B1
公开(公告)日：2004-10-12
申请号：US09880458
申请日：2001-06-12
申请人： Roger May , Igor Kostarnov , Edward H. Flaherty , Mark Dickinson
发明人： Roger May , Igor Kostarnov , Edward H. Flaherty , Mark Dickinson
IPC分类号： H03K190177
CPC分类号： G06F15/7867
摘要： The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.
摘要翻译：本发明提供了用于在芯片的可编程逻辑部分和嵌入式处理器部分之间共享I / O引脚的电路和方法。可编程逻辑部分和嵌入式处理器部分中的电路可以访问数据信号并将数据信号发送到相同的I / O引脚。数据信号被复用以控制对共享I / O引脚的访问。多路复用器可以由控制信号控制，该控制信号确定特定的I / O引脚何时由可编程逻辑部分和嵌入式处理器部分访问。将相关的I / O引脚电路配置为正确I / O标准的控制信号也由本发明的共享I / O电路复用。在发送到嵌入式处理器部分的共享I / O引脚处接收到的信号可以被同时发送到可编程逻辑部分内的监听电路。

10. 发明授权

US07343483B1 Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream 有权
标题翻译：使用单个串行化配置位流来配置可编程逻辑器件及其嵌入式逻辑
公开(公告)号：US07343483B1
公开(公告)日：2008-03-11
申请号：US10792407
申请日：2004-03-02
申请人： Roger May , Andrew Draper
发明人： Roger May , Andrew Draper
IPC分类号： G06F15/177
CPC分类号： G06F13/405
摘要： A method and apparatus for configuring a digital system having a programmable logic device and embedded logic from a configuration source that supplies a single serialized configuration bit stream for configuring both the programmable logic device and the embedded logic.
摘要翻译：一种用于配置具有可编程逻辑器件和嵌入式逻辑的数字系统的方法和装置，该配置源提供用于配置可编程逻辑器件和嵌入式逻辑的单个串行化配置位流。

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