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1. 发明授权

US08709833B2 Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations 失效
标题翻译：使用组合二极管/电阻器结构测量电流和电阻，以监控集成电路制造工艺的变化
公开(公告)号：US08709833B2
公开(公告)日：2014-04-29
申请号：US13334632
申请日：2011-12-22
申请人： Lyndon R. Logan , Edward J. Nowak , Robert R. Robison , Jonathan K. Winslow, II
发明人： Lyndon R. Logan , Edward J. Nowak , Robert R. Robison , Jonathan K. Winslow, II
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L23/58 , G01R19/0092 , G01R27/14 , H01L22/30 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
摘要翻译：使用可操作地连接到计算机化机器的制造设备，在集成电路结构内形成多个二极管/电阻器件。每个二极管/电阻器件包括集成到单个结构中的二极管器件和电阻器件。在使用可操作地连接到计算机化机器的测试设备来测试集成电路结构时测量每个二极管/电阻器件的电阻。在使用测试设备的集成电路结构测试期间，也测量通过每个二极管/电阻器件的电流。然后，根据集成电路结构内的晶体管器件的特性的变化和/或集成电路结构内的晶体管器件的制造工艺的变化来计算电阻和电流的响应曲线。

2. 发明授权

US08652922B2 Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture 有权
标题翻译：紧凑的热控薄膜电阻器，利用基板触点和制造方法
公开(公告)号：US08652922B2
公开(公告)日：2014-02-18
申请号：US13008459
申请日：2011-01-18
申请人： Joseph M. Lukaitis , Jed H. Rankin , Robert R. Robison , Dustin K. Slisher , Timothy D. Sullivan
发明人： Joseph M. Lukaitis , Jed H. Rankin , Robert R. Robison , Dustin K. Slisher , Timothy D. Sullivan
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L27/0207 , H01L27/1203
摘要： A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate and forming a trench in the resistor and into the substrate. The method also includes forming a liner on sidewalls of the trench and forming a core comprising a high thermal conductivity material in the trench and on the liner.
摘要翻译：形成半导体结构的方法包括在衬底上的绝缘体层上形成电阻器，并在电阻器中形成沟槽并进入衬底。该方法还包括在沟槽的侧壁上形成衬垫，并在沟槽和衬垫上形成包括高导热性材料的芯。

3. 发明授权

US08637871B2 Asymmetric hetero-structure FET and method of manufacture 有权
标题翻译：非对称异质结构FET及其制造方法
公开(公告)号：US08637871B2
公开(公告)日：2014-01-28
申请号：US12939462
申请日：2010-11-04
申请人： Brent A. Anderson , Jeffrey B. Johnson , Edward J. Nowak , Robert R. Robison
发明人： Brent A. Anderson , Jeffrey B. Johnson , Edward J. Nowak , Robert R. Robison
IPC分类号： H01L29/15
CPC分类号： H01L29/1054 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66659
摘要： An asymmetric hetero-structure FET and method of manufacture is provided. The structure includes a semiconductor substrate and an epitaxially grown semiconductor layer on the semiconductor substrate. The epitaxially grown semiconductor layer includes an alloy having a band structure and thickness that confines inversion carriers in a channel region, and a thicker portion extending deeper into the semiconductor structure at a doped edge to avoid confinement of the inversion carriers at the doped edge.
摘要翻译：提供了非对称异质结构FET及其制造方法。该结构包括在半导体衬底上的半导体衬底和外延生长的半导体层。外延生长的半导体层包括具有限制沟道区域中的反转载流子的带结构和厚度的合金，以及在掺杂边缘处更深地延伸到半导体结构中的较厚部分，以避免在掺杂边缘处限制反转载流子。

4. 发明授权

US08610211B2 Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure 有权
标题翻译：绝缘体上半导体（SOI）结构，具有选择性放置的亚绝缘体层空穴和形成SOI结构的方法
公开(公告)号：US08610211B2
公开(公告)日：2013-12-17
申请号：US12842146
申请日：2010-07-23
申请人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
发明人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
IPC分类号： H01L27/12
CPC分类号： H01L29/66477 , H01L21/02104 , H01L21/84 , H01L27/1203 , H01L29/78648 , H01L29/78654
摘要： Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.
摘要翻译：公开了一种绝缘体半导体（SOI）结构，其具有选择性地放置在衬底中的次绝缘体层空穴，使得半导体层的第一部分与衬底之间的电容耦合将小于第二半导体层和衬底的截面。第一部分可以包含绝缘体层上的第一器件，第二部分可以在绝缘体层上包含第二器件。或者，第一和第二部分可以包括绝缘体层上相同器件的不同区域。例如，在SOI场效应晶体管（FET）中，可以将子绝缘体层空隙选择性地放置在源极，漏极和/或体接触扩散区域下方的衬底中，但不能在沟道区域下方，使得电容耦合这些各种扩散区域和衬底将小于沟道区域和衬底之间的电容耦合。此外，公开了形成这种SOI结构的相关方法。

5. 发明申请

US20130161615A1 MEASURING CURRENT AND RESISTANCE USING COMBINED DIODES/RESISTOR STRUCTURE TO MONITOR INTEGRATED CIRCUIT MANUFACTURING PROCESS VARIATIONS 失效
标题翻译：使用组合二极管/电阻结构测量电流和电阻监视集成电路制造过程变化
公开(公告)号：US20130161615A1
公开(公告)日：2013-06-27
申请号：US13334632
申请日：2011-12-22
申请人： Lyndon R. Logan , Edward J. Nowak , Robert R. Robison , Jonathan K. Winslow, II
发明人： Lyndon R. Logan , Edward J. Nowak , Robert R. Robison , Jonathan K. Winslow, II
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L23/58 , G01R19/0092 , G01R27/14 , H01L22/30 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.
摘要翻译：使用可操作地连接到计算机化机器的制造设备，在集成电路结构内形成多个二极管/电阻器件。每个二极管/电阻器件包括集成到单个结构中的二极管器件和电阻器件。在使用可操作地连接到计算机化机器的测试设备来测试集成电路结构时测量每个二极管/电阻器件的电阻。在使用测试设备的集成电路结构测试期间，也测量通过每个二极管/电阻器件的电流。然后，根据集成电路结构内的晶体管器件的特性的变化和/或集成电路结构内的晶体管器件的制造工艺的变化来计算电阻和电流的响应曲线。

6. 发明授权

US08460981B2 Use of contacts to create differential stresses on devices 有权
公开(公告)号：US08460981B2
公开(公告)日：2013-06-11
申请号：US12892465
申请日：2010-09-28
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
IPC分类号： H01L21/00
CPC分类号： H01L21/76879 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/092
摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.

7. 发明申请

US20110115054A1 SEMISPHERICAL INTEGRATED CIRCUIT STRUCTURES 有权
标题翻译：半导体集成电路结构
公开(公告)号：US20110115054A1
公开(公告)日：2011-05-19
申请号：US12621956
申请日：2009-11-19
申请人： Kangguo Cheng , Toshiharu Furukawa , Robert R. Robison , William R. Tonti , Richard Q. Williams
发明人： Kangguo Cheng , Toshiharu Furukawa , Robert R. Robison , William R. Tonti , Richard Q. Williams
IPC分类号： H01L29/73 , H01L29/06 , H01L21/331
CPC分类号： H01L31/03529 , H01L27/14643 , H01L29/0657 , H01L29/6609 , H01L29/66136 , H01L29/66234 , H01L29/732 , H01L29/8611 , H01L29/868 , H01L31/0352 , H01L31/103 , Y02E10/50
摘要： A diode comprises a substrate formed of a first material having a first doping polarity. The substrate has a planar surface and at least one semispherical structure extending from the planar surface. The semispherical structure is formed of the first material. A layer of second material is over the semispherical structure. The second material comprises a second doping polarity opposite the first doping polarity. The layer of second material conforms to the shape of the semispherical structure. A first electrical contact is connected to the substrate, and a second electrical contact is connected to the layer of second material. Additional semiconductor structures are formed by fabricating additional layers over the original layers.
摘要翻译：二极管包括由具有第一掺杂极性的第一材料形成的衬底。衬底具有平坦表面和从平面表面延伸的至少一个半球形结构。半球形结构由第一材料形成。第二材料层在半球形结构之上。第二材料包括与第一掺杂极性相反的第二掺杂极性。第二材料层符合半球形结构的形状。第一电触头连接到基板，第二电触点连接到第二材料层。通过在原始层上制造附加层来形成附加的半导体结构。

8. 发明申请

US20110101506A1 Stress Memorization Technique Using Silicon Spacer 审中-公开
标题翻译：应用记忆技术使用硅垫片
公开(公告)号：US20110101506A1
公开(公告)日：2011-05-05
申请号：US12608107
申请日：2009-10-29
申请人： Shahid A. Butt , Viorel Ontalus , Robert R. Robison
发明人： Shahid A. Butt , Viorel Ontalus , Robert R. Robison
IPC分类号： H01L29/06 , H01L21/31 , H01L23/58
CPC分类号： H01L29/7847 , H01L29/6653
摘要： A structure for memorizing tensile stress in a semiconductor device includes a gate electrode of the semiconductor device; a silicon spacer adjacent to the gate electrode; and a capping layer encapsulating the gate electrode and the silicon spacer, wherein the silicon spacer and capping layer are configured to cause a tensile stress to be memorized in the gate electrode during an annealing process. A method for memorizing tensile stress in a semiconductor device includes forming a silicon spacer adjacent to a gate electrode of the semiconductor device; forming a capping layer over the silicon spacer and the gate electrode; and annealing the semiconductor device, wherein the silicon spacer and capping layer cause a tensile stress to be memorized in the gate electrode during annealing. A disposable silicon spacer is configured to induce a tensile stress in a semiconductor device during a stress memorization technique process.
摘要翻译：用于在半导体器件中记忆拉伸应力的结构包括半导体器件的栅电极; 与栅电极相邻的硅间隔物; 以及封装所述栅电极和所述硅间隔物的覆盖层，其中所述硅间隔物和覆盖层被配置为在退火过程期间使拉应力存储在所述栅电极中。一种用于记忆半导体器件中的拉伸应力的方法包括：形成与所述半导体器件的栅电极相邻的硅间隔物; 在所述硅间隔物和所述栅电极上形成覆盖层; 并退火所述半导体器件，其中所述硅衬垫和封盖层在退火期间使拉应力存储在所述栅电极中。一次性硅衬垫构造成在应力记忆技术过程中在半导体器件中引起拉伸应力。

9. 发明申请

US20110089499A1 STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES 有权
公开(公告)号：US20110089499A1
公开(公告)日：2011-04-21
申请号：US12581924
申请日：2009-10-20
申请人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
发明人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/66545 , H01L29/66659
摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

10. 发明授权

US07808039B2 SOI transistor with merged lateral bipolar transistor 失效
标题翻译：具有合并横向双极晶体管的SOI晶体管
公开(公告)号：US07808039B2
公开(公告)日：2010-10-05
申请号：US12099879
申请日：2008-04-09
申请人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
发明人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
IPC分类号： H01L27/088
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/0722
摘要： A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.
摘要翻译：绝缘体上半导体晶体管器件包括源极区，漏极区，体区和源极横向双极晶体管。源区具有第一导电类型。体区具有第二导电类型并且位于源区和漏区之间。源极横向双极晶体管包括基极，集电极和发射极。硅化物区将基底连接到收集器。发射器是身体区域。集电体具有第二导电类型，基极是源极区，位于发射极和集电极之间。

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