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1. 发明申请

US20110053372A1 Low Temperature Surface Preparation for Removal of Organometallic Polymers in the Manufacture of Integrated Circuits 审中-公开
标题翻译：用于去除有机金属聚合物的低温表面准备在集成电路的制造中
公开(公告)号：US20110053372A1
公开(公告)日：2011-03-03
申请号：US12549538
申请日：2009-08-28
申请人： Srinivas Raghavan , Kalyan Cherukuri , Murlidhar Bashyam , Richard A. Faust
发明人： Srinivas Raghavan , Kalyan Cherukuri , Murlidhar Bashyam , Richard A. Faust
IPC分类号： H01L21/3205
CPC分类号： H01L21/0206 , H01L21/31133 , H01L21/32139 , H01L28/60
摘要： A method of removing photoresist from a surface during the manufacture of an integrated circuit. Organometallic polymers and monomers are formed during the etch of a hard mask material defining the locations of a metal-bearing film, such as tantalum nitride, when photoresist is used to mask the hard mask etch. These organometallic polymers and monomers as formed are not fully cross-linked. A liquid phase solution of sulfuric acid and hydrogen peroxide used to remove the photoresist also removes these not-fully-cross-linked organometallic polymers and monomers, thus preventing the formation of stubborn contaminants during subsequent high temperature processing.
摘要翻译：在制造集成电路期间从表面去除光致抗蚀剂的方法。在光刻胶用于掩蔽硬掩模蚀刻时，在蚀刻期间限定含金属膜（例如氮化钽）的位置的硬掩模材料的蚀刻期间形成有机金属聚合物和单体。形成的这些有机金属聚合物和单体不完全交联。用于除去光致抗蚀剂的硫酸和过氧化氢的液相溶液也可除去这些不完全交联的有机金属聚合物和单体，从而防止在随后的高温处理期间形成顽固的污染物。

2. 发明申请

US20110306207A1 METHOD OF FABRICATING METAL-BEARING INTEGRATED CIRCUIT STRUCTURES HAVING LOW DEFECT DENSITY 有权
标题翻译：制造具有低缺陷密度的金属轴承集成电路结构的方法
公开(公告)号：US20110306207A1
公开(公告)日：2011-12-15
申请号：US12816381
申请日：2010-06-15
申请人： Srinivas Raghavan , Kalyan Cherukuri , Thomas E. Lillibridge , Richard A. Faust
发明人： Srinivas Raghavan , Kalyan Cherukuri , Thomas E. Lillibridge , Richard A. Faust
IPC分类号： H01L21/3205
CPC分类号： H01L28/40 , H01L21/0206 , H01L21/31116 , H01L21/31133 , H01L21/32134 , H01L21/32139
摘要： A method of fabricating metal-bearing structures in an integrated circuit such as metal-polysilicon capacitors using conductive metal compounds. Defects due to organometallic polymers formed during the etch of a hard mask material are minimized by using a process that includes a plasma etch for the hard mask that achieves a predominantly chemical character using a fluorine-based etch chemistry. Using a low-temperature liquid-phase strip of the hard mask photoresist instead of an ash prevents further cross-linking of polymers formed during the plasma etch. Etching the metal-bearing material using a hot fully-concentrated mixture of ammonium hydroxide and hydrogen peroxide allows short etch times that are particularly shortened for tantalum nitride films deposited with a nitrogen concentration of about 30 percent or greater.
摘要翻译：一种在集成电路中制造含金属结构的方法，例如使用导电金属化合物的金属 - 多晶硅电容器。通过使用包括使用氟基蚀刻化学物质实现主要化学特征的硬掩模的等离子体蚀刻的方法，使在硬掩模材料的蚀刻期间形成的有机金属聚合物的缺陷最小化。使用硬掩模光刻胶的低温液相条带代替灰分防止在等离子体蚀刻期间形成的聚合物的进一步交联。使用氢氧化铵和过氧化氢的热的完全浓缩的混合物来蚀刻含金属材料允许短时间的蚀刻时间，其特别地缩短了以大约30％或更大的氮浓度沉积的氮化钽膜。

3. 发明授权

US07655555B2 In-situ co-deposition of Si in diffusion barrier material depositions with improved wettability, barrier efficiency, and device reliability 有权
标题翻译：在扩散阻挡材料沉积中Si的原位共沉积，具有改善的润湿性，阻隔效率和器件可靠性
公开(公告)号：US07655555B2
公开(公告)日：2010-02-02
申请号：US09895520
申请日：2001-06-28
申请人： Richard A. Faust , Qing-Tang Jiang , Jiong-Ping Lu
发明人： Richard A. Faust , Qing-Tang Jiang , Jiong-Ping Lu
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/28
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/76807 , H01L21/76843
摘要： A copper interconnect having a transition metal-silicon-nitride barrier (106). A transition metal-nitride is co-deposited with Si by reactive sputtering in a Si containing ambient to form barrier (106). The copper (110) is then deposited over the transition metal-silicon-nitride barrier (108) with good adhesion.
摘要翻译：具有过渡金属 - 氮化硅屏障（106）的铜互连。过渡金属氮化物通过在含Si环境中的反应性溅射与Si共沉积以形成势垒（106）。然后，铜（110）以良好的粘附性沉积在过渡金属 - 氮化硅屏障（108）上。

4. 发明申请

US20090170305A1 METHOD FOR IMPROVING ELECTROMIGRATION LIFETIME FOR CU INTERCONNECT SYSTEMS 审中-公开
标题翻译：改进CU互连系统电寿命的方法
公开(公告)号：US20090170305A1
公开(公告)日：2009-07-02
申请号：US12047485
申请日：2008-03-13
申请人： Jeffrey A. West , Richard A. Faust , Srinivasa Raghavan
发明人： Jeffrey A. West , Richard A. Faust , Srinivasa Raghavan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76886 , H01L21/76808 , H01L21/76834 , H01L21/76883
摘要： A method for forming a single damascene and/or dual damascene interconnect structure, comprising: performing front end processing, depositing copper, annealing the copper, performing CMP planarization, performing a post copper CMP clean process, performing a BTA rinse, performing IPA drying process, performing doping during thermal ramp up and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌互连结构的方法，包括：执行前端处理，沉积铜，退火铜，执行CMP平坦化，执行后铜CMP清洁工艺，进行BTA漂洗，进行IPA干燥过程在加热过程中进行掺杂并执行剩余的后端处理。

5. 发明授权

US08258041B2 Method of fabricating metal-bearing integrated circuit structures having low defect density 有权
标题翻译：制造具有低缺陷密度的金属轴承集成电路结构的方法
公开(公告)号：US08258041B2
公开(公告)日：2012-09-04
申请号：US12816381
申请日：2010-06-15
申请人： Srinivas Raghavan , Kalyan Cherukuri , Thomas E. Lillibridge , Richard A. Faust
发明人： Srinivas Raghavan , Kalyan Cherukuri , Thomas E. Lillibridge , Richard A. Faust
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L21/0206 , H01L21/31116 , H01L21/31133 , H01L21/32134 , H01L21/32139
摘要： A method of fabricating metal-bearing structures in an integrated circuit such as metal-polysilicon capacitors using conductive metal compounds. Defects due to organometallic polymers formed during the etch of a hard mask material are minimized by using a process that includes a plasma etch for the hard mask that achieves a predominantly chemical character using a fluorine-based etch chemistry. Using a low-temperature liquid-phase strip of the hard mask photoresist instead of an ash prevents further cross-linking of polymers formed during the plasma etch. Etching the metal-bearing material using a hot fully-concentrated mixture of ammonium hydroxide and hydrogen peroxide allows short etch times that are particularly shortened for tantalum nitride films deposited with a nitrogen concentration of about 30 percent or greater.
摘要翻译：一种在集成电路中制造含金属结构的方法，例如使用导电金属化合物的金属 - 多晶硅电容器。通过使用包括使用氟基蚀刻化学物质实现主要化学特征的硬掩模的等离子体蚀刻的方法，使在硬掩模材料的蚀刻期间形成的有机金属聚合物的缺陷最小化。使用硬掩模光刻胶的低温液相条带代替灰分防止在等离子体蚀刻期间形成的聚合物的进一步交联。使用氢氧化铵和过氧化氢的热的完全浓缩的混合物来蚀刻含金属材料允许短时间的蚀刻时间，其特别地缩短了以大约30％或更大的氮浓度沉积的氮化钽膜。

6. 发明授权

US07215000B2 Selectively encased surface metal structures in a semiconductor device 有权
标题翻译：在半导体器件中选择性地封装表面金属结构
公开(公告)号：US07215000B2
公开(公告)日：2007-05-08
申请号：US10924346
申请日：2004-08-23
申请人： Richard A. Faust , Young-Joon Park
发明人： Richard A. Faust , Young-Joon Park
IPC分类号： H01L29/00 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5227 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides, in one embodiment, An integrated circuit device (100). The integrated circuit device (100) comprises a circuit feature (105) located over a semiconductor substrate (110) and an insulating layer (115) located over the circuit feature (105). A protective overcoat (120) is located over the insulating layer (115) and a metal structure (125) is located over the protective overcoat (120). The metal structure (125) is electrically connected to the circuit feature (105) by an interconnect (130). The metal structure (125) is coated with a conductive encasement (135), the conductive encasement (135) terminating at a perimeter (140) of the metal structure (125). Another embodiment of the invention in a method of manufacturing an integrated circuit device (200).
摘要翻译：本发明在一个实施例中提供一种集成电路装置（100）。集成电路器件（100）包括位于半导体衬底（110）之上的电路特征（105）和位于电路特征（105）之上的绝缘层（115）。保护性外涂层（120）位于绝缘层（115）上方，并且金属结构（125）位于保护外涂层（120）上方。金属结构（125）通过互连（130）电连接到电路特征（105）。金属结构（125）涂覆有导电封套（135），导电封套（135）终止于金属结构（125）的周边（140）。在制造集成电路器件（200）的方法中本发明的另一个实施例。

7. 发明授权

US06958290B2 Method and apparatus for improving adhesion between layers in integrated devices 有权
标题翻译：用于改善集成装置中的层之间的附着力的方法和装置
公开(公告)号：US06958290B2
公开(公告)日：2005-10-25
申请号：US10138393
申请日：2002-05-03
申请人： Richard A. Faust, Jr. , Qing-Tang Jiang , Jiong-Ping Lu
发明人： Richard A. Faust, Jr. , Qing-Tang Jiang , Jiong-Ping Lu
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/532 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： In an integrated device, a via is formed in a substrate layer and a barrier layer is formed on the substrate layer in the via. A seed layer is formed on the barrier layer in the via. The seed layer includes a first material and a second material. The first material provides an ability for the second material to maintain an adherence to the barrier layer.
摘要翻译：在集成器件中，在衬底层中形成通孔，并且在通孔中的衬底层上形成阻挡层。在通孔的阻挡层上形成种子层。种子层包括第一材料和第二材料。第一种材料提供了使第二种材料保持与阻挡层粘合的能力。

8. 发明授权

US06720255B1 Semiconductor device with silicon-carbon-oxygen dielectric having improved metal barrier adhesion and method of forming the device 有权
标题翻译：具有改善的金属屏障粘附性的硅 - 碳 - 氧电介质的半导体器件和形成该器件的方法
公开(公告)号：US06720255B1
公开(公告)日：2004-04-13
申请号：US10318309
申请日：2002-12-12
申请人： Richard A. Faust , Noel M. Russell , Li Chen
发明人： Richard A. Faust , Noel M. Russell , Li Chen
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/76804 , H01L21/76814 , H01L21/76826 , H01L21/76831
摘要： A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a dielectric layer (226) in a fixed position relative to the wafer, where the dielectric layer comprises an atomic concentration of each of silicon, carbon, and oxygen. After the forming step, the method exposes (118) the electronic device to a plasma such that the atomic concentration of carbon in a portion of the dielectric layer is increased and the atomic concentration of oxygen in a portion of the dielectric layer is decreased. After the exposing step, the method forms a barrier layer (120) adjacent at least a portion of the dielectric layer.
摘要翻译：一种制造形成在半导体晶片上的电子器件（200）的方法（100）。该方法形成相对于晶片处于固定位置的介电层（226），其中介电层包括硅，碳和氧各自的原子浓度。在形成步骤之后，该方法将电子器件暴露（118）到等离子体，使得电介质层的一部分中的碳的原子浓度增加，并且介电层的一部分中的氧的原子浓度降低。在曝光步骤之后，该方法形成与电介质层的至少一部分相邻的阻挡层（120）。

9. 发明授权

US06680249B2 Si-rich surface layer capped diffusion barriers 有权
标题翻译：富硅表面层封端扩散阻挡层
公开(公告)号：US06680249B2
公开(公告)日：2004-01-20
申请号：US10185383
申请日：2002-06-28
申请人： Jiong-Ping Lu , Wei-Yung Hsu , Qi-Zhong Hong , Richard A. Faust
发明人： Jiong-Ping Lu , Wei-Yung Hsu , Qi-Zhong Hong , Richard A. Faust
IPC分类号： H01L2144
CPC分类号： H01L21/2855 , H01L21/76807 , H01L21/76843 , H01L21/76846 , H01L21/76856
摘要： A copper interconnect having a transition metal-nitride barrier (106) with a thin metal-silicon-nitride cap (108). A transition metal-nitride barrier (106) is formed over the structure. Then the barrier (106) is annealed in a Si-containing ambient to form a silicon-rich capping layer (108) at the surface of the barrier (106). The copper (110) is then deposited over the silicon-rich capping layer (108) with good adhesion.
摘要翻译：一种具有过渡金属氮化物屏障（106）与铜金属 - 氮化硅帽（108）的铜互连。在该结构上形成过渡金属氮化物屏障（106）。然后，阻挡层（106）在含Si环境中退火，以在阻挡层（106）的表面形成富含硅的覆盖层（108）。然后，铜（110）以良好的粘合力沉积在富含硅的覆盖层（108）上。

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