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1. 发明授权

US6107641A Thin film transistor with reduced parasitic capacitance and reduced feed-through voltage 失效
标题翻译：具有降低的寄生电容和降低的馈通电压的薄膜晶体管
公开(公告)号：US6107641A
公开(公告)日：2000-08-22
申请号：US927023
申请日：1997-09-10
申请人： Ping Mei , Rene A. Lujan , James B. Boyce , Christopher L. Chua , Michael G. Hack
发明人： Ping Mei , Rene A. Lujan , James B. Boyce , Christopher L. Chua , Michael G. Hack
IPC分类号： H01L21/223 , H01L21/225 , H01L21/266 , H01L21/336 , H01L27/144 , H01L27/146 , H01L29/786 , H01L31/0216 , H01L29/76
CPC分类号： H01L29/78696 , H01L21/223 , H01L21/2236 , H01L21/2254 , H01L21/2255 , H01L21/266 , H01L27/1443 , H01L27/14603 , H01L29/66757 , H01L29/66765 , H01L29/78669 , H01L31/02162 , H01L31/02165 , Y10S438/94
摘要： An improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser doping technique is applied to fabricate such transistors. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.
摘要翻译：提供了不具有源极/栅极或漏极/栅极重叠的改进的薄膜晶体管结构。应用激光掺杂技术来制造这种晶体管。消除源极/栅极和漏极/栅极重叠显着降低或消除了源极和栅极之间的寄生电容和馈通电压。可以获得具有高场效应迁移率的短沟道a-Si：H薄膜晶体管。提供了改进的像素性能和像素到像素的均匀性。

2. 发明授权

US6020223A Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage 失效
公开(公告)号：US6020223A
公开(公告)日：2000-02-01
申请号：US959590
申请日：1997-10-29
申请人： Ping Mei , Rene A. Lujan , James B. Boyce , Christopher L. Chua , Michael G. Hack
发明人： Ping Mei , Rene A. Lujan , James B. Boyce , Christopher L. Chua , Michael G. Hack
IPC分类号： H01L21/223 , H01L21/225 , H01L21/266 , H01L21/336 , H01L27/144 , H01L27/146 , H01L29/786 , H01L31/0216 , H01L21/00 , H01L21/84
CPC分类号： H01L29/78696 , H01L21/223 , H01L21/2236 , H01L21/2254 , H01L21/2255 , H01L21/266 , H01L27/1443 , H01L27/14603 , H01L29/66757 , H01L29/66765 , H01L29/78669 , H01L31/02162 , H01L31/02165 , Y10S438/94
摘要： A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.

3. 发明授权

US06019796A Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage 失效
标题翻译：制造具有降低的寄生电容和降低的馈通电压的薄膜晶体管的方法
公开(公告)号：US06019796A
公开(公告)日：2000-02-01
申请号：US960025
申请日：1997-10-29
申请人： Ping Mei , Rene A. Lujan , James B. Boyce , Christopher L. Chua , Michael G. Hack
发明人： Ping Mei , Rene A. Lujan , James B. Boyce , Christopher L. Chua , Michael G. Hack
IPC分类号： H01L21/223 , H01L21/225 , H01L21/266 , H01L21/336 , H01L27/144 , H01L27/146 , H01L29/786 , H01L31/0216 , H01L21/00
CPC分类号： H01L29/78696 , H01L21/223 , H01L21/2236 , H01L21/2254 , H01L21/2255 , H01L21/266 , H01L27/1443 , H01L27/14603 , H01L29/66757 , H01L29/66765 , H01L29/78669 , H01L31/02162 , H01L31/02165 , Y10S438/94
摘要： A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.
摘要翻译：提供了不具有源极/栅极或漏极/栅极重叠的制造改进的薄膜晶体管结构的方法。应用激光辅助掺杂技术来制造这种晶体管。使用辐射滤光器，其在光刻波长下对光是透明的，但在激光波长处是反射的或不透明的。消除源极/栅极和漏极/栅极重叠显着降低或消除了源极和栅极之间的寄生电容和馈通电压。可以获得具有高场效应迁移率的短沟道a-Si：H薄膜晶体管。提供了改进的像素性能和像素到像素的均匀性。

4. 发明授权

US5366926A Low temperature process for laser dehydrogenation and crystallization of amorphous silicon 失效
标题翻译：用于激光脱氢和非晶硅结晶的低温工艺
公开(公告)号：US5366926A
公开(公告)日：1994-11-22
申请号：US073022
申请日：1993-06-07
申请人： Ping Mei , James B. Boyce , Richard I. Johnson , Michael G. Hack , Rene A. Lujan
发明人： Ping Mei , James B. Boyce , Richard I. Johnson , Michael G. Hack , Rene A. Lujan
IPC分类号： H01L21/20 , H01L21/26
CPC分类号： H01L21/2026 , Y10S148/09 , Y10S148/093
摘要： A low temperature process for dehydrogenating amorphous silicon using lasers. Dehydrogenation occurs by irradiating one or more areas of a hydrogenated amorphous silicon layer with laser beam pulses at a relatively low energy density. After the multiple laser pulse irradiation at a relatively low energy density, the laser energy density is increased and multiple irradiation at a higher energy density is performed. If after the multiple irradiation at the higher energy density the amorphous silicon hydrogen content is still too high, dehydrogenation proceeds by multiple irradiations at a yet higher energy density. The irradiation at the various energy densities can result in the formation of polysilicon due to melting of the amorphous silicon layer. As irradiation may be selectively applied to the amorphous silicon, an integral amorphous silicon-polysilicon structure may be formed.
摘要翻译：使用激光使非晶硅脱氢的低温工艺。通过以相对低的能量密度用激光束脉冲照射氢化非晶硅层的一个或多个区域来进行脱氢。在相对低能量密度的多次激光脉冲照射之后，激光能量密度增加，并且以更高的能量密度进行多次照射。如果在较高能量密度下的多次照射之后，非晶硅氢含量仍然太高，则以更高的能量密度进行多次照射进行脱氢。在各种能量密度下的照射可导致由于非晶硅层的熔化而形成多晶硅。当照射可以选择性地施加到非晶硅时，可以形成整体的非晶硅 - 多晶硅结构。

5. 发明授权

US5871826A Proximity laser doping technique for electronic materials 失效
标题翻译：电子材料接近激光掺杂技术
公开(公告)号：US5871826A
公开(公告)日：1999-02-16
申请号：US655549
申请日：1996-05-30
申请人： Ping Mei , Rene A. Lujan , James B. Boyce
发明人： Ping Mei , Rene A. Lujan , James B. Boyce
IPC分类号： H01L21/20 , H01L21/22 , H01L21/223 , H01L21/225 , H01L21/268 , H01L21/30 , H01L21/336 , H01L21/8238 , B05D3/06
CPC分类号： H01L29/66757 , H01L21/22 , H01L21/2225 , H01L21/223 , H01L21/2233 , H01L21/2252 , H01L21/3003 , H01L21/823871 , H01L21/2026
摘要： This invention relates to a method of altering the electrical characteristics of a material through a laser ablation process. It can achieve high doping levels and shallow junctions at low temperatures, which are desirable in the fabrication of thin film transistors.
摘要翻译：本发明涉及通过激光烧蚀工艺改变材料的电特性的方法。它可以在低温下实现高掺杂水平和浅结，这在薄膜晶体管的制造中是期望的。

6. 发明授权

US5733804A Fabricating fully self-aligned amorphous silicon device 失效
标题翻译：制造完全自对准非晶硅器件
公开(公告)号：US5733804A
公开(公告)日：1998-03-31
申请号：US577634
申请日：1995-12-22
申请人： Michael G. Hack , Rene A. Lujan
发明人： Michael G. Hack , Rene A. Lujan
IPC分类号： H01L21/336 , H01L21/77 , H01L21/84 , H01L29/786
CPC分类号： H01L29/78696 , H01L27/1214 , H01L29/66765 , Y10S438/949
摘要： An amorphous silicon thin film transistor (a-Si TFT) or other a-Si device is produced by depositing and lithographically patterning a layer of doped semiconductor material such as microcrystalline or polycrystalline silicon to produce a conductive lead. The semiconductor material is deposited over an insulating region and over an exposed part of an amorphous silicon layer. The insulating region has an edge that is over and approximately aligned with an edge of a gate region. The doped semiconductor layer therefore forms a junction to the amorphous silicon layer at the edge of the insulating region, approximately aligned with the edge of the gate region. Self-aligned lithographic patterning is performed in such a way that the conductive lead overlaps the insulating region by a distance that is no more than a maximum overlap distance. The maximum overlap distance can, for example, be no more than 1.0 .mu.m, and can be 0.5 .mu.m. The insulating region and the doped semiconductor layer can both be lithographically patterned by a combination of self-aligned backside exposure and top masked exposure. Overlap distance can be controlled by timing backside exposure, application of developer, baking, or application of etchant.
摘要翻译：通过对诸如微晶或多晶硅的掺杂半导体材料的层进行沉积和光刻图案来制造非晶硅薄膜晶体管（a-Si TFT）或其它a-Si器件，以产生导电引线。半导体材料沉积在非晶硅层的绝缘区域和暴露部分之上。绝缘区域具有在栅极区域的边缘上方且大致对齐的边缘。因此，掺杂半导体层在绝缘区域的边缘处形成大致与栅极区域的边缘对准的非晶硅层的结。以这样的方式进行自对准平版印刷图案，使得导电引线与绝缘区域重叠不超过最大重叠距离的距离。最大重叠距离例如可以不大于1.0μm，并且可以是0.5μm。绝缘区域和掺杂半导体层可以通过自对准背面曝光和顶部掩模曝光的组合进行光刻图案化。重叠距离可以通过定时背面曝光，显影剂的应用，烘烤或蚀刻剂的应用来控制。

7. 发明授权

US5717223A Array with amorphous silicon TFTs in which channel leads overlap insulating region no more than maximum overlap 失效
标题翻译：具有非晶硅TFT的阵列，其中沟道引线重叠绝缘区不超过最大重叠
公开(公告)号：US5717223A
公开(公告)日：1998-02-10
申请号：US578780
申请日：1995-12-22
申请人： Michael G. Hack , Rene A. Lujan
发明人： Michael G. Hack , Rene A. Lujan
IPC分类号： G02F1/136 , G02F1/1368 , H01L21/336 , H01L27/12 , H01L29/786 , H01L29/04
CPC分类号： H01L29/78696 , H01L27/12 , H01L29/66765 , G02F1/1368 , H01L29/78618 , H01L29/78669
摘要： An array includes cells, each with a bottom gate amorphous silicon thin film transistor (a-Si TFT). Each a-Si TFT has an undoped amorphous silicon layer over its gate region and extending beyond its edges. Each a-Si TFT also has an insulating region with edges approximately aligned with the edges of its gate region. Two channel leads of doped semiconductor material such as microcrystalline silicon or polycrystalline silicon are on the undoped amorphous silicon layer, each overlapping an edge of the insulating region by a distance that is no more than a maximum overlap distance, which in turn is no more than 1.0 .mu.m.
摘要翻译：阵列包括具有底栅非晶硅薄膜晶体管（a-Si TFT）的单元。每个a-Si TFT在其栅极区域上具有未掺杂的非晶硅层并且延伸超过其边缘。每个a-Si TFT还具有绝缘区域，其边缘与其栅极区域的边缘大致对准。掺杂半导体材料如微晶硅或多晶硅的两通道引线位于未掺杂的非晶硅层上，每个引线与绝缘区域的边缘重叠不超过最大重叠距离的距离，其不超过 1.0亩

8. 发明授权

US6140668A Silicon structures having an absorption layer 失效
标题翻译：具有吸收层的硅结构
公开(公告)号：US6140668A
公开(公告)日：2000-10-31
申请号：US69055
申请日：1998-04-28
申请人： Ping Mei , Rene A. Lujan
发明人： Ping Mei , Rene A. Lujan
IPC分类号： H01L21/77 , H01L21/84 , H01L27/12 , H01L29/76 , H01L29/04
CPC分类号： H01L27/1214
摘要： Amorphous and polycrystalline silicon (hybrid) devices are formed close to one another employing laser crystallization and back side lithography processes. A mask (e.g., TiW) is used to protect the amorphous silicon device during laser crystallization. A patterned nitride layer is used to protect the amorphous silicon device during rehydrogenation of the polycrystalline silicon. An absorption film (e.g., amorphous silicon) is used to compensate for the different transparencies of amorphous and polycrystalline silicon during the back side lithography. Device spacing of between 2 and 50 micrometers may be obtained, while using materials and process steps otherwise compatible with existing hybrid device formation processes.
摘要翻译：使用激光结晶和背面光刻工艺，非晶和多晶硅（混合）器件彼此靠近地形成。在激光结晶期间，使用掩模（例如TiW）来保护非晶硅器件。在多晶硅的再氢化期间，使用图案化的氮化物层来保护非晶硅器件。吸收膜（例如，非晶硅）用于补偿背面光刻期间的非晶硅和多晶硅的不同透明度。可以获得2至50微米之间的器件间隔，同时使用与现有的混合器件形成工艺相适应的材料和工艺步骤。

9. 发明授权

US06504175B1 Hybrid polycrystalline and amorphous silicon structures on a shared substrate 失效
标题翻译：共享衬底上的混合多晶和非晶硅结构
公开(公告)号：US06504175B1
公开(公告)日：2003-01-07
申请号：US09067943
申请日：1998-04-28
申请人： Ping Mei , Rene A. Lujan
发明人： Ping Mei , Rene A. Lujan
IPC分类号： H01L2976
CPC分类号： H01L27/1237 , H01L27/1214 , H01L27/1274 , H01L28/20 , H01L29/66757 , H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/94
摘要： Amorphous and polycrystalline silicon (hybrid) devices are formed close to one another employing laser crystallization and back side lithography processes. A mask (e.g., TiW) is used to protect the amorphous silicon device during laser crystallization. A patterned nitride layer is used to protect the amorphous silicon device during rehydrogenation of the polycrystalline silicon. An absorption film (e.g., amorphous silicon) is used to compensate for the different transparencies of amorphous and polycrystalline silicon during the back side lithography. Device spacing of between 2 and 50 micrometers may be obtained, while using materials and process steps otherwise compatible with existing hybrid device formation processes.
摘要翻译：使用激光结晶和背面光刻工艺，非晶和多晶硅（混合）器件彼此靠近地形成。在激光结晶期间，使用掩模（例如TiW）来保护非晶硅器件。在多晶硅的再氢化期间，使用图案化的氮化物层来保护非晶硅器件。吸收膜（例如，非晶硅）用于补偿背面光刻期间的非晶硅和多晶硅的不同透明度。可以获得2至50微米之间的器件间隔，同时使用与现有的混合器件形成工艺相适应的材料和工艺步骤。

10. 发明申请

US20090159940A1 STRUCTURE AND METHOD FOR FLEXIBLE SENSOR ARRAY 有权
标题翻译：柔性传感器阵列的结构和方法
公开(公告)号：US20090159940A1
公开(公告)日：2009-06-25
申请号：US11963008
申请日：2007-12-21
申请人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
发明人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14658 , H01L27/14692
摘要： A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.
摘要翻译：一种形成传感器阵列的方法。该方法包括沉积源极/漏极接触层; 在源极/漏极接触层上沉积半导体层; 并且基本上同时构图源极/漏极接触层和半导体层，其中图案化的半导体层形成传感器阵列的传感器的一部分。

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