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1. 发明授权

US06237086B1 1 Method to prevent pipeline stalls in superscalar stack based computing systems 失效
标题翻译： 1在基于超标量堆栈的计算系统中防止管道停顿的方法
公开(公告)号：US06237086B1
公开(公告)日：2001-05-22
申请号：US09064807
申请日：1998-04-22
申请人： Sailendra Koppala , Ravinandan R. Buchamwandla
发明人： Sailendra Koppala , Ravinandan R. Buchamwandla
IPC分类号： G06F938
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/322 , G06F9/38 , G06F9/3824 , G06F9/3853 , G06F9/3861
摘要： An execution unit for a stack based computing system that can combine instructions into instruction groups for concurrent execution is provided. In accordance with one embodiment, the instructions of the stack based computing system are separated into different instruction types. Certain combinations of instruction types can be combined into instruction groups for concurrent execution. The execution unit includes an instruction folding unit that is configured to determine the instruction type of instructions and combine the instructions into instruction groups, and an instruction pipeline that is configured to process both instructions and instruction groups. In one embodiment, the instruction folding unit includes: an instruction type estimator which estimates the instruction types of various instructions; an instruction selector, which selects the instruction types from the estimated instruction types; and a folding logic circuit which combines the instructions into instruction groups.
摘要翻译：提供了一种用于基于堆栈的计算系统的执行单元，其可以将指令组合成用于并发执行的指令组。根据一个实施例，基于栈的计算系统的指令被分成不同的指令类型。指令类型的某些组合可以组合成用于并发执行的指令组。执行单元包括指令折叠单元，其被配置为确定指令的指令类型并将指令组合成指令组，以及被配置为处理指令和指令组两者的指令流水线。在一个实施例中，指令折叠单元包括：估计各种指令的指令类型的指令类型估计器; 指令选择器，其从所述估计指令类型中选择所述指令类型; 以及将指令组合到指令组中的折叠逻辑电路。

2. 发明授权

US07610431B1 Configuration space compaction 有权
标题翻译：配置空间压缩
公开(公告)号：US07610431B1
公开(公告)日：2009-10-27
申请号：US11250731
申请日：2005-10-14
申请人： John Watkins , Ola Tørudbakken , John Petry , Michelle L Wong , Ravinandan R Buchamwandla
发明人： John Watkins , Ola Tørudbakken , John Petry , Michelle L Wong , Ravinandan R Buchamwandla
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： In an interconnect apparatus for interconnecting at least one host to at least a plurality of presentation registers provide a presentation interface for the device to the host. The interconnect apparatus includes memory for holding the presentation registers and a governor operable to manage the presentation registers in the memory.
摘要翻译：在用于将至少一个主机与至少多个呈现寄存器互连的互连装置中，为主机提供该设备的呈现接口。互连装置包括用于保持呈现寄存器的存储器和可操作以管理存储器中的呈现寄存器的调节器。

3. 发明授权

US06275903B1 Stack cache miss handling 失效
标题翻译：堆栈缓存未命中处理
公开(公告)号：US06275903B1
公开(公告)日：2001-08-14
申请号：US09064686
申请日：1998-04-22
申请人： Sailendra Koppala , Ravinandan R. Buchamwandla
发明人： Sailendra Koppala , Ravinandan R. Buchamwandla
IPC分类号： G06F1208
CPC分类号： G06F9/30134 , G06F9/3824 , G06F9/3853 , G06F9/3861 , G06F12/0875
摘要： An instruction pipeline is provided which can handle stack cache misses without stalling. The instruction pipeline includes a stack cache fetch stage configured to retrieve data from a stack cache and a data cache fetch stage configured to retrieve data from a data cache. The instruction pipeline writes data out during a write stage that occurs at the end of the instruction pipeline. Thus, instead of stalling on a stack cache miss, the instruction pipeline can continue processing and issuing a data cache request in the data cache fetch stage for the required data. In addition, some embodiments of the invention include a feedback path between the stack cache fetch stage and pipeline stages following the stack cache fetch stage. If the stack cache fetch stage requires data from an address that is also being used by a later pipeline stage, the data in the later pipeline stage is sent to the stack cache fetch stage through the feedback path.
摘要翻译：提供了可以处理堆栈高速缓存未命中而不停滞的指令流水线。指令流水线包括被配置为从堆栈高速缓存检索数据的堆栈高速缓存提取阶段和被配置为从数据高速缓存检索数据的数据高速缓存提取阶段。指令流水线在指令流水线末尾发生的写入阶段写入数据。因此，指令流水线不是在堆栈高速缓存未命中停止，而是可以在数据高速缓存提取阶段继续处理和发出所需数据的数据高速缓存请求。此外，本发明的一些实施例包括在堆栈高速缓存提取阶段之后的堆栈高速缓存提取级和流水线级之间的反馈路径。如果堆栈高速缓存提取阶段需要来自也被稍后流水线阶段使用的地址的数据，则后期流水线阶段中的数据将通过反馈路径发送到堆栈高速缓存提取阶段。

4. 发明授权

US06170050A Length decoder for variable length data 失效
标题翻译：长度解码器用于可变长度数据
公开(公告)号：US06170050A
公开(公告)日：2001-01-02
申请号：US09064680
申请日：1998-04-22
申请人： Sailendra Koppala , Ravinandan R. Buchamwandla
发明人： Sailendra Koppala , Ravinandan R. Buchamwandla
IPC分类号： G06F930
CPC分类号： G06F9/382 , G06F9/30134 , G06F9/30149 , G06F9/3822 , G06F9/3824 , G06F9/3853 , G06F9/3861
摘要： A length decoder that rapidly calculates the group lengths of groups of variable length data words is provided. In accordance with one embodiment, a length decoder includes a length estimator and a length selector. The length estimator, estimates a length for each data word assuming the data word is the first member of a group. The length selector then selects the proper estimate based upon the actual length of the data word. Specifically, one embodiment of the length decoder can be used to calculate the length of instruction groups in a stack based computing system.
摘要翻译：提供了一种快速计算可变长度数据字组的组长度的长度解码器。根据一个实施例，一个长度解码器包括一个长度估计器和一个长度选择器。长度估计器估计每个数据字的长度，假设数据字是组的第一个成员。然后，长度选择器基于数据字的实际长度来选择适当的估计。具体地，可以使用长度解码器的一个实施例来计算基于堆栈的计算系统中的指令组的长度。

5. 发明授权

US6108768A Reissue logic for individually reissuing instructions trapped in a multiissue stack based computing system 失效
标题翻译：重发逻辑，用于单独重新发布基于多重堆栈的计算系统中的指令
公开(公告)号：US6108768A
公开(公告)日：2000-08-22
申请号：US64642
申请日：1998-04-22
申请人： Sailendra Koppala , Ravinandan R. Buchamwandla
发明人： Sailendra Koppala , Ravinandan R. Buchamwandla
IPC分类号： G06F9/30 , G06F9/38 , G06F9/40
CPC分类号： G06F9/382 , G06F9/30134 , G06F9/30149 , G06F9/322 , G06F9/3822 , G06F9/3824 , G06F9/3861
摘要： An execution unit that executes multiple instructions as a single instruction group during a single processing cycle is provided. The execution unit handles problem causing instruction groups by trapping the problem causing instruction group using the trap logic of a processing unit. The reissue logic circuits restores the program state of the execution unit prior to issuance of the trapped instruction group. The reissue logic circuit then forces each instruction of the instruction group to be issued as a separate instruction. Specifically, the reissue logic inhibits folding of instructions into instruction groups by an instruction-folding unit. After the instructions of the trapped instruction group are executed, the reissue logic re-enables folding by the instruction-folding unit.
摘要翻译：提供了在单个处理周期期间作为单个指令组执行多个指令的执行单元。执行单元通过使用处理单元的陷阱逻辑捕获引起问题的指令组来处理引起问题的指令组。再发行逻辑电路在被捕获的指令组发出之前恢复执行单元的编程状态。然后，重发逻辑电路强制指令组的每个指令作为单独的指令发出。具体地说，重发逻辑禁止指令折叠单元将指令折叠成指令组。在执行被捕获的指令组的指令之后，重新发行逻辑重新启用指令折叠单元的折叠。

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