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1. 发明授权

US6167488A Stack caching circuit with overflow/underflow unit 失效
标题翻译：具有溢出/下溢单元的堆栈缓存电路
公开(公告)号：US6167488A
公开(公告)日：2000-12-26
申请号：US828899
申请日：1997-03-31
申请人： Sailendra Koppala
发明人： Sailendra Koppala
IPC分类号： G06F7/78 , G06F12/08 , G06F12/12
CPC分类号： G06F7/785 , G06F12/0875
摘要： The present invention provides a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit suspends operation of the stack cache and causes the spill control unit to store the valid data words in the slow memory unit or data cache unit. After the valid data in the stack cache are saved, the overflow/underflow unit equates the cache bottom pointer to the optop pointer. The overflow/underflow unit then resumes normal operation of the stack cache. If an underflow occurs, the overflow/underflow unit suspends operation of the stack cache. In most underflow conditions, data in stack cache 255 are no longer valid and are not saved. Therefore, the overflow/underflow equates the cache bottom pointer to the optop pointer and resumes operation of the stack cache. For underflows caused by context switches, the data in the stack cache must be saved.
摘要翻译：本发明提供了一种堆栈管理单元，其包括堆栈高速缓存，用于加速从栈的数据检索和将数据存储到栈中。在一个实施例中，堆栈管理单元包括堆栈高速缓存，运球管理器单元和堆栈控制单元。运球管理器单元维护缓存的堆栈部分，通常是堆栈高速缓存中堆栈的顶部。堆栈高速缓存包括堆栈高速缓冲存储器电路，一个或多个读取端口以及一个或多个写入端口。堆栈管理单元还包括溢出/下溢单元。溢出/下溢单元检测并解决溢出条件和下溢条件。如果发生溢出，溢出/下溢单元暂停堆栈高速缓存的操作，并使溢出控制单元将有效数据字存储在慢速存储单元或数据高速缓存单元中。在保存堆栈高速缓存中的有效数据之后，溢出/下溢单元将缓存底部指针等同于optop指针。溢出/下溢单元然后恢复堆栈高速缓存的正常操作。如果发生下溢，溢出/下溢单元挂起堆栈高速缓存的操作。在大多数下溢条件下，堆栈高速缓存255中的数据不再有效，不能保存。因此，溢出/下溢将缓存底部指针等同于optop指针，并恢复堆栈高速缓存的操作。对于由上下文切换引起的下溢，必须保存堆栈缓存中的数据。

2. 发明授权

US6131144A Stack caching method with overflow/underflow control using pointers 失效
标题翻译：堆栈缓存方法，使用指针进行溢出/下溢控制
公开(公告)号：US6131144A
公开(公告)日：2000-10-10
申请号：US828769
申请日：1997-04-01
申请人： Sailendra Koppala
发明人： Sailendra Koppala
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0875
摘要： The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit resolves the overflow by suspending operation of the stack cache and spilling a plurality of data words from the stack cache to the stack and equating the bottom pointer to the optop pointer. Typically, the overflow/underflow unit spills all valid data words from the stack cache during an overflow. If an underflow occurs during a context switch the overflow/underflow unit resolves the underflow by spilling a plurality of data word from the stack cache to the stack and equating the bottom pointer to the optop pointer. If an underflow without a context switch the overflow/underflow unit resolves the underflow by equating the bottom pointer to the optop pointer.
摘要翻译：本发明使用包括堆栈高速缓存的堆栈管理单元来加速从栈的数据检索和数据存储到堆栈中。在一个实施例中，堆栈管理单元包括堆栈高速缓存，运球管理器单元和堆栈控制单元。运球管理器单元维护缓存的堆栈部分，通常是堆栈高速缓存中堆栈的顶部。堆栈高速缓存包括堆栈高速缓冲存储器电路，一个或多个读取端口以及一个或多个写入端口。堆栈管理单元还包括溢出/下溢单元。溢出/下溢单元检测并解决溢出条件和下溢条件。如果溢出发生溢出/下溢单元通过暂停堆栈高速缓存的操作来解决溢出，并将多个数据字从堆栈缓存溢出到堆栈，并将底部指针与optop指针相等。通常，溢出/下溢单元在溢出期间溢出来自堆栈高速缓存的所有有效数据字。如果在上下文切换期间发生下溢，则溢出/下溢单元通过将多个数据字从堆栈缓存溢出到堆栈并将底部指针等同于optop指针来解决下溢。如果没有上下文切换的下溢，则溢出/下溢单元通过将底部指针与optop指针相等来解决下溢。

3. 发明授权

US06289418B1 Address pipelined stack caching method 失效
标题翻译：地址流水线堆栈缓存方法
公开(公告)号：US06289418B1
公开(公告)日：2001-09-11
申请号：US08829105
申请日：1997-03-31
申请人： Sailendra Koppala
发明人： Sailendra Koppala
IPC分类号： G06F1208
CPC分类号： G06F9/30134 , G06F12/0875 , G06F2212/451
摘要： The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an address pipeline to transfer multiple data words by the spill control unit and the fill control unit to improve the throughput of spill and fill operations. When new data words are written to the top memory location of the stack, the optop pointer is incremented. If data words are read off the stack the optop pointer is decremented. During normal operations the dribble manager unit detects spill conditions and fill conditions. If a spill condition occurs, the dribble manager unit spills a plurality of data words from the stack cache to the stack. If a fill condition occurs, the dribble manager unit fills a plurality of data words from the stack to the stack cache.
摘要翻译：本发明使用包括堆栈高速缓存的堆栈管理单元来加速从栈的数据检索和数据存储到堆栈中。在一个实施例中，堆栈管理单元包括堆栈高速缓存，运球管理器单元和堆栈控制单元。运球管理器单元维护缓存的堆栈部分，通常是堆栈高速缓存中堆栈的顶部。堆栈高速缓存包括堆栈高速缓冲存储器电路，一个或多个读取端口以及一个或多个写入端口。堆栈管理单元还包括通过溢出控制单元和填充控制单元传送多个数据字的地址管线，以提高溢出和填充操作的吞吐量。当新数据字被写入堆栈的顶部存储单元时，optop指针递增。如果从堆栈读取数据字，则optop指针递减。运行管理员在正常操作期间检测溢出条件和填充条件。如果发生溢出情况，运球管理器单元将多个数据字从堆栈高速缓存溢出到堆栈。如果发生填充条件，则运球管理器单元将堆叠中的多个数据字填充到堆栈高速缓存。

4. 发明授权

US06237086B1 1 Method to prevent pipeline stalls in superscalar stack based computing systems 失效
标题翻译： 1在基于超标量堆栈的计算系统中防止管道停顿的方法
公开(公告)号：US06237086B1
公开(公告)日：2001-05-22
申请号：US09064807
申请日：1998-04-22
申请人： Sailendra Koppala , Ravinandan R. Buchamwandla
发明人： Sailendra Koppala , Ravinandan R. Buchamwandla
IPC分类号： G06F938
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/322 , G06F9/38 , G06F9/3824 , G06F9/3853 , G06F9/3861
摘要： An execution unit for a stack based computing system that can combine instructions into instruction groups for concurrent execution is provided. In accordance with one embodiment, the instructions of the stack based computing system are separated into different instruction types. Certain combinations of instruction types can be combined into instruction groups for concurrent execution. The execution unit includes an instruction folding unit that is configured to determine the instruction type of instructions and combine the instructions into instruction groups, and an instruction pipeline that is configured to process both instructions and instruction groups. In one embodiment, the instruction folding unit includes: an instruction type estimator which estimates the instruction types of various instructions; an instruction selector, which selects the instruction types from the estimated instruction types; and a folding logic circuit which combines the instructions into instruction groups.
摘要翻译：提供了一种用于基于堆栈的计算系统的执行单元，其可以将指令组合成用于并发执行的指令组。根据一个实施例，基于栈的计算系统的指令被分成不同的指令类型。指令类型的某些组合可以组合成用于并发执行的指令组。执行单元包括指令折叠单元，其被配置为确定指令的指令类型并将指令组合成指令组，以及被配置为处理指令和指令组两者的指令流水线。在一个实施例中，指令折叠单元包括：估计各种指令的指令类型的指令类型估计器; 指令选择器，其从所述估计指令类型中选择所述指令类型; 以及将指令组合到指令组中的折叠逻辑电路。

5. 发明授权

US6009499A Pipelined stack caching circuit 失效
标题翻译：流水线堆栈缓存电路
公开(公告)号：US6009499A
公开(公告)日：1999-12-28
申请号：US831279
申请日：1997-03-31
申请人： Sailendra Koppala
发明人： Sailendra Koppala
IPC分类号： G06F7/78 , G06F12/08 , G06F9/06
CPC分类号： G06F7/785 , G06F12/0875
摘要： A stack management unit includes a stack cache to accelerate data retrieval from a stack and data storage into the stack. The stack management unit also includes an address pipeline to transfer multiple data words by a spill control unit and a fill control unit in the stack management unit. The address pipeline contains an incrementor/decrementor circuit, a first address register and a second address register. An address multiplexer drives either the output signal of the incrementor/decrementor or a cache bottom pointer to the first address register. The output terminals of the first address register are coupled to the input terminals of the second address register. A stack cache multiplexer drives either the address in the first address register or the address in the second address register to the stack cache. A memory multiplexer drives either the address in the address multiplexer or in the first address register to a slow memory unit. The address in the second address register can be used to adjust the value of the cache bottom pointer.
摘要翻译：堆栈管理单元包括堆栈高速缓存，用于加速从栈的数据检索和将数据存储到栈中。堆栈管理单元还包括通过溢出控制单元和堆栈管理单元中的填充控制单元传送多个数据字的地址管线。地址管道包含一个递增器/递减器电路，一个第一地址寄存器和一个第二地址寄存器。地址多路复用器驱动增量器/递减器的输出信号或缓冲器底部指针到第一地址寄存器。第一地址寄存器的输出端耦合到第二地址寄存器的输入端。堆栈高速缓存多路复用器将第一地址寄存器中的地址或第二地址寄存器中的地址驱动到堆栈高速缓存。存储器多路复用器将地址多路复用器中的地址或第一地址寄存器中的地址驱动到慢速存储器单元。第二个地址寄存器中的地址可用于调整缓存底部指针的值。

6. 发明授权

US06275903B1 Stack cache miss handling 失效
标题翻译：堆栈缓存未命中处理
公开(公告)号：US06275903B1
公开(公告)日：2001-08-14
申请号：US09064686
申请日：1998-04-22
申请人： Sailendra Koppala , Ravinandan R. Buchamwandla
发明人： Sailendra Koppala , Ravinandan R. Buchamwandla
IPC分类号： G06F1208
CPC分类号： G06F9/30134 , G06F9/3824 , G06F9/3853 , G06F9/3861 , G06F12/0875
摘要： An instruction pipeline is provided which can handle stack cache misses without stalling. The instruction pipeline includes a stack cache fetch stage configured to retrieve data from a stack cache and a data cache fetch stage configured to retrieve data from a data cache. The instruction pipeline writes data out during a write stage that occurs at the end of the instruction pipeline. Thus, instead of stalling on a stack cache miss, the instruction pipeline can continue processing and issuing a data cache request in the data cache fetch stage for the required data. In addition, some embodiments of the invention include a feedback path between the stack cache fetch stage and pipeline stages following the stack cache fetch stage. If the stack cache fetch stage requires data from an address that is also being used by a later pipeline stage, the data in the later pipeline stage is sent to the stack cache fetch stage through the feedback path.
摘要翻译：提供了可以处理堆栈高速缓存未命中而不停滞的指令流水线。指令流水线包括被配置为从堆栈高速缓存检索数据的堆栈高速缓存提取阶段和被配置为从数据高速缓存检索数据的数据高速缓存提取阶段。指令流水线在指令流水线末尾发生的写入阶段写入数据。因此，指令流水线不是在堆栈高速缓存未命中停止，而是可以在数据高速缓存提取阶段继续处理和发出所需数据的数据高速缓存请求。此外，本发明的一些实施例包括在堆栈高速缓存提取阶段之后的堆栈高速缓存提取级和流水线级之间的反馈路径。如果堆栈高速缓存提取阶段需要来自也被稍后流水线阶段使用的地址的数据，则后期流水线阶段中的数据将通过反馈路径发送到堆栈高速缓存提取阶段。

7. 发明授权

US06170050A Length decoder for variable length data 失效
标题翻译：长度解码器用于可变长度数据
公开(公告)号：US06170050A
公开(公告)日：2001-01-02
申请号：US09064680
申请日：1998-04-22
申请人： Sailendra Koppala , Ravinandan R. Buchamwandla
发明人： Sailendra Koppala , Ravinandan R. Buchamwandla
IPC分类号： G06F930
CPC分类号： G06F9/382 , G06F9/30134 , G06F9/30149 , G06F9/3822 , G06F9/3824 , G06F9/3853 , G06F9/3861
摘要： A length decoder that rapidly calculates the group lengths of groups of variable length data words is provided. In accordance with one embodiment, a length decoder includes a length estimator and a length selector. The length estimator, estimates a length for each data word assuming the data word is the first member of a group. The length selector then selects the proper estimate based upon the actual length of the data word. Specifically, one embodiment of the length decoder can be used to calculate the length of instruction groups in a stack based computing system.
摘要翻译：提供了一种快速计算可变长度数据字组的组长度的长度解码器。根据一个实施例，一个长度解码器包括一个长度估计器和一个长度选择器。长度估计器估计每个数据字的长度，假设数据字是组的第一个成员。然后，长度选择器基于数据字的实际长度来选择适当的估计。具体地，可以使用长度解码器的一个实施例来计算基于堆栈的计算系统中的指令组的长度。

8. 发明授权

US6108768A Reissue logic for individually reissuing instructions trapped in a multiissue stack based computing system 失效
标题翻译：重发逻辑，用于单独重新发布基于多重堆栈的计算系统中的指令
公开(公告)号：US6108768A
公开(公告)日：2000-08-22
申请号：US64642
申请日：1998-04-22
申请人： Sailendra Koppala , Ravinandan R. Buchamwandla
发明人： Sailendra Koppala , Ravinandan R. Buchamwandla
IPC分类号： G06F9/30 , G06F9/38 , G06F9/40
CPC分类号： G06F9/382 , G06F9/30134 , G06F9/30149 , G06F9/322 , G06F9/3822 , G06F9/3824 , G06F9/3861
摘要： An execution unit that executes multiple instructions as a single instruction group during a single processing cycle is provided. The execution unit handles problem causing instruction groups by trapping the problem causing instruction group using the trap logic of a processing unit. The reissue logic circuits restores the program state of the execution unit prior to issuance of the trapped instruction group. The reissue logic circuit then forces each instruction of the instruction group to be issued as a separate instruction. Specifically, the reissue logic inhibits folding of instructions into instruction groups by an instruction-folding unit. After the instructions of the trapped instruction group are executed, the reissue logic re-enables folding by the instruction-folding unit.
摘要翻译：提供了在单个处理周期期间作为单个指令组执行多个指令的执行单元。执行单元通过使用处理单元的陷阱逻辑捕获引起问题的指令组来处理引起问题的指令组。再发行逻辑电路在被捕获的指令组发出之前恢复执行单元的编程状态。然后，重发逻辑电路强制指令组的每个指令作为单独的指令发出。具体地说，重发逻辑禁止指令折叠单元将指令折叠成指令组。在执行被捕获的指令组的指令之后，重新发行逻辑重新启用指令折叠单元的折叠。

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