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1. 发明申请

US20140359230A1 PROTOCOL FOR CONFLICTING MEMORY TRANSACTIONS 有权
标题翻译：冲突内存交易协议
公开(公告)号：US20140359230A1
公开(公告)日：2014-12-04
申请号：US13997900
申请日：2011-12-20
申请人： Manoj K. Arora , Robert G. Blankenship , Rahul Pal , Dheemanth Nagaraj
发明人： Manoj K. Arora , Robert G. Blankenship , Rahul Pal , Dheemanth Nagaraj
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0824 , G06F12/0828 , G06F12/0831 , G06F13/14 , G06F13/38
摘要： Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions.Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.
摘要翻译：本发明的实施例描述了高速缓存一致性协议，其消除了在消息类之间排序的需要，并且还消除了家庭跟踪器预分配。与现有技术的解决方案相比，本发明的实施例描述了一种不太复杂的冲突检测和解决机制（在归属代理），与带宽或延迟形式没有任何性能下降。本发明的实施例描述了可以接收诸如数据所有权请求消息和数据请求消息的请求消息的归属代理，其包括指示所发出的各个消息的顺序的发布数据。所述归属代理可以至少部分地基于接收到的冲突响应消息和最近完成的交易的发行数据来确定是否存在早期或晚期冲突。

2. 发明授权

US08862828B2 Sub-numa clustering 有权
标题翻译：亚类聚类
公开(公告)号：US08862828B2
公开(公告)日：2014-10-14
申请号：US13584656
申请日：2012-08-13
申请人： Ravindra P. Saraf , Rahul Pal , Ashok Jagannathan
发明人： Ravindra P. Saraf , Rahul Pal , Ashok Jagannathan
IPC分类号： G06F12/08
CPC分类号： G06F12/0692
摘要： Method and apparatus to efficiently store and cache data. Cores of a processor and cache slices co-located with the cores may be grouped into a cluster. A memory space may be partitioned into address regions. The cluster may be associated with an address region from the address regions. Each memory address of the address region may be mapped to one or more of the cache slices grouped into the cluster. A cache access from one or more of the cores grouped into the cluster may be biased to the address region based on the association of the cluster with the address region.
摘要翻译：有效存储和缓存数据的方法和装置。处理器的核心和与核心共处的缓存片段可以被分组成一个群集。存储器空间可以被分割成地址区域。集群可以与地址区域的地址区域相关联。可以将地址区域的每个存储器地址映射到分组到集群中的一个或多个高速缓存片段。基于群集与地址区域的关联，可以将分组到群集中的一个或多个核心的高速缓存访问偏移到地址区域。

3. 发明申请

US20120131282A1 Providing A Directory Cache For Peripheral Devices 失效
标题翻译：为外围设备提供目录缓存
公开(公告)号：US20120131282A1
公开(公告)日：2012-05-24
申请号：US12953120
申请日：2010-11-23
申请人： Andrew Y. Sun , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Ravindra P. Saraf
发明人： Andrew Y. Sun , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Ravindra P. Saraf
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有至少一个核和非逻辑逻辑的处理器。非逻辑逻辑可以包括用作控制对存储器区域的访问的保护的归属代理。在归属代理或非逻辑逻辑的另一部分中，可以提供目录高速缓存以存储由耦合到处理器的代理拥有的存储器区域的一部分的所有权信息。以这种方式，当存储器区域的访问请求在目录高速缓存中丢失时，可以避免存储器事务。描述和要求保护其他实施例。

4. 发明申请

US20060271822A1 Method and system for quantifying the quality of diagnostic software 有权
标题翻译：用于量化诊断软件质量的方法和系统
公开(公告)号：US20060271822A1
公开(公告)日：2006-11-30
申请号：US11138734
申请日：2005-05-26
申请人： Rahul Pal , Kumar Vadhri , Gulam Dastagir
发明人： Rahul Pal , Kumar Vadhri , Gulam Dastagir
IPC分类号： G06F11/00
CPC分类号： G06F11/261
摘要： A method, a system, and an apparatus for quantification of the quality of diagnostic software by applying a coverage tool are provided, wherein the diagnostic software is used for testing a computing system. The method involves executing the diagnostic software in an Integrated Circuit (IC) verification environment. The diagnostic software is executed by a Virtual Computer-processing Unit (V-CPU), which models (Central Processing Unit) CPU of the computing system to be tested.
摘要翻译：提供了一种通过应用覆盖工具来量化诊断软件的质量的方法，系统和装置，其中诊断软件用于测试计算系统。该方法涉及在集成电路（IC）验证环境中执行诊断软件。诊断软件由要测试的计算系统的型号（中央处理单元）CPU的虚拟计算机处理单元（V-CPU）执行。

5. 发明申请

US20220269433A1 SYSTEM, METHOD AND APPARATUS FOR PEER-TO-PEER COMMUNICATION 有权
公开(公告)号：US20220269433A1
公开(公告)日：2022-08-25
申请号：US17682015
申请日：2022-02-28
申请人： Rahul Pal , Susanne M. Balle , David Puffer , Nagabhushan Chitlur
发明人： Rahul Pal , Susanne M. Balle , David Puffer , Nagabhushan Chitlur
IPC分类号： G06F3/06
摘要： In an embodiment, an apparatus includes: a first downstream port to couple to a first peer device; a second downstream port to couple to a second peer device; and a peer-to-peer (PTP) circuit to receive a memory access request from the first peer device, the memory access request having a target associated with the second peer device, where the PTP circuit is to convert the memory access request from a coherent protocol to a memory protocol and send the converted memory access request to the second peer device. Other embodiments are described and claimed.

6. 发明申请

US20220014202A1 Three-Dimensional Stacked Programmable Logic Fabric and Processor Design Architecture 有权
公开(公告)号：US20220014202A1
公开(公告)日：2022-01-13
申请号：US17485119
申请日：2021-09-24
申请人： Rahul Pal , Dheeraj Subbareddy , Mahesh Kumashikar , Dheemanth Nagaraj , Rajesh Vivekanandham , Anshuman Thakur , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
发明人： Rahul Pal , Dheeraj Subbareddy , Mahesh Kumashikar , Dheemanth Nagaraj , Rajesh Vivekanandham , Anshuman Thakur , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
IPC分类号： H03K19/17796 , G06F15/78 , G06F30/34 , H03K19/17758
摘要： The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.

7. 发明申请

US20210042254A1 ACCELERATOR CONTROLLER HUB 有权
公开(公告)号：US20210042254A1
公开(公告)日：2021-02-11
申请号：US17083200
申请日：2020-10-28
申请人： Pratik Marolia , Andrew Herdrich , Rajesh Sankaran , Rahul Pal , David Puffer , Sayantan Sur , Ajaya Durg
发明人： Pratik Marolia , Andrew Herdrich , Rajesh Sankaran , Rahul Pal , David Puffer , Sayantan Sur , Ajaya Durg
IPC分类号： G06F13/40 , G06F13/42
摘要： Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

8. 发明申请

US20160092366A1 METHOD AND APPARATUS FOR DISTRIBUTED SNOOP FILTERING 有权
标题翻译：用于分布式SNOOP过滤的方法和装置
公开(公告)号：US20160092366A1
公开(公告)日：2016-03-31
申请号：US14497740
申请日：2014-09-26
申请人： Rahul PAL , Ishwar AGARWAL , Yen-Cheng LIU , Joseph NUZMAN , Ashok JAGANNATHAN , Bahaa FAHIM , Nithiyanandan BASHYAM
发明人： Rahul PAL , Ishwar AGARWAL , Yen-Cheng LIU , Joseph NUZMAN , Ashok JAGANNATHAN , Bahaa FAHIM , Nithiyanandan BASHYAM
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F12/0831 , G06F2212/452
摘要： An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC.
摘要翻译：描述了一种用于分布式监听过滤的设备和方法。例如，处理器的一个实施例包括：执行指令和处理数据的多个核; 第一侦听逻辑，用于跟踪存储在由一个或多个核可访问的中级高速缓存（“MLC”）中的第一多个高速缓存行，所述第一侦听逻辑用于为存储在所述MLC中的高速缓存行分配条目，并且取消分配条目对于从MLC移出的高速缓存行，其中从MLC中逐出的至少一些高速缓存行保留在级别1（L1）高速缓存中; 和第二窥探逻辑，用于跟踪存储在非包容性最后一级高速缓存（NI LLC）中的第二多个高速缓存行，所述第二监听逻辑用于在所述NI LLC中分配用于从所述MLC驱逐的高速缓存行的条目，并且取消分配用于高速缓存的条目存储在MLC中的行，其中第二侦听逻辑将存储和维护第一组核心有效位以识别包含存储在NI LLC中的高速缓存行的副本的内核。

9. 发明申请

US20140006715A1 SUB-NUMA CLUSTERING 有权
标题翻译： SUB-NUMA聚集
公开(公告)号：US20140006715A1
公开(公告)日：2014-01-02
申请号：US13584656
申请日：2012-08-13
申请人： Ravindra P. Saraf , Rahul Pal , Ashok Jagannathan
发明人： Ravindra P. Saraf , Rahul Pal , Ashok Jagannathan
IPC分类号： G06F12/08
CPC分类号： G06F12/0692
摘要： Method and apparatus to efficiently store and cache data. Cores of a processor and cache slices co-located with the cores may be grouped into a cluster. A memory space may be partitioned into address regions. The cluster may be associated with an address region from the address regions. Each memory address of the address region may be mapped to one or more of the cache slices grouped into the cluster. A cache access from one or more of the cores grouped into the cluster may be biased to the address region based on the association of the cluster with the address region.
摘要翻译：有效存储和缓存数据的方法和装置。处理器的核心和与核心共处的缓存片段可以被分组成一个群集。存储器空间可以被分割成地址区域。集群可以与地址区域的地址区域相关联。可以将地址区域的每个存储器地址映射到分组到集群中的一个或多个高速缓存片段。基于群集与地址区域的关联，可以将分组到群集中的一个或多个核心的高速缓存访问偏移到地址区域。

10. 发明授权

US08489822B2 Providing a directory cache for peripheral devices 失效
标题翻译：为外围设备提供目录缓存
公开(公告)号：US08489822B2
公开(公告)日：2013-07-16
申请号：US12953120
申请日：2010-11-23
申请人： Andrew Y. Sun , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Ravindra P. Saraf
发明人： Andrew Y. Sun , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Ravindra P. Saraf
IPC分类号： G06F13/00
CPC分类号： G06F12/0817
摘要： In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有至少一个核和非逻辑逻辑的处理器。非逻辑逻辑可以包括用作控制对存储器区域的访问的保护的归属代理。在归属代理或非逻辑逻辑的另一部分中，可以提供目录高速缓存以存储由耦合到处理器的代理拥有的存储器区域的一部分的所有权信息。以这种方式，当存储器区域的访问请求在目录高速缓存中丢失时，可以避免存储器事务。描述和要求保护其他实施例。

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