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1. 发明授权

US09235520B2 Protocol for conflicting memory transactions 有权
标题翻译：内存交易冲突的协议
公开(公告)号：US09235520B2
公开(公告)日：2016-01-12
申请号：US13997900
申请日：2011-12-20
申请人： Manoj K. Arora , Robert G. Blankenship , Rahul Pal , Dheemanth Nagaraj
发明人： Manoj K. Arora , Robert G. Blankenship , Rahul Pal , Dheemanth Nagaraj
IPC分类号： G06F12/00 , G06F12/08 , G06F13/14 , G06F13/38
CPC分类号： G06F12/0815 , G06F12/0824 , G06F12/0828 , G06F12/0831 , G06F13/14 , G06F13/38
摘要： Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions.Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.
摘要翻译：本发明的实施例描述了高速缓存一致性协议，其消除了在消息类之间排序的需要，并且还消除了家庭跟踪器预分配。与现有技术的解决方案相比，本发明的实施例描述了一种不太复杂的冲突检测和解决机制（在归属代理），与带宽或延迟形式没有任何性能下降。本发明的实施例描述了可以接收诸如数据所有权请求消息和数据请求消息的请求消息的归属代理，其包括指示所发出的各个消息的顺序的发布数据。所述归属代理可以至少部分地基于接收到的冲突响应消息和最近完成的交易的发行数据来确定是否存在早期或晚期冲突。

2. 发明申请

US20140359230A1 PROTOCOL FOR CONFLICTING MEMORY TRANSACTIONS 有权
标题翻译：冲突内存交易协议
公开(公告)号：US20140359230A1
公开(公告)日：2014-12-04
申请号：US13997900
申请日：2011-12-20
申请人： Manoj K. Arora , Robert G. Blankenship , Rahul Pal , Dheemanth Nagaraj
发明人： Manoj K. Arora , Robert G. Blankenship , Rahul Pal , Dheemanth Nagaraj
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0824 , G06F12/0828 , G06F12/0831 , G06F13/14 , G06F13/38
摘要： Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions.Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.
摘要翻译：本发明的实施例描述了高速缓存一致性协议，其消除了在消息类之间排序的需要，并且还消除了家庭跟踪器预分配。与现有技术的解决方案相比，本发明的实施例描述了一种不太复杂的冲突检测和解决机制（在归属代理），与带宽或延迟形式没有任何性能下降。本发明的实施例描述了可以接收诸如数据所有权请求消息和数据请求消息的请求消息的归属代理，其包括指示所发出的各个消息的顺序的发布数据。所述归属代理可以至少部分地基于接收到的冲突响应消息和最近完成的交易的发行数据来确定是否存在早期或晚期冲突。

3. 发明申请

US20120047333A1 EXTENDING A CACHE COHERENCY SNOOP BROADCAST PROTOCOL WITH DIRECTORY INFORMATION 失效
标题翻译：扩展带有目录信息的高速缓存的SNOOP广播协议
公开(公告)号：US20120047333A1
公开(公告)日：2012-02-23
申请号：US12860340
申请日：2010-08-20
申请人： SAILESH KOTTAPALLI , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Dheemanth Nagaraj
发明人： SAILESH KOTTAPALLI , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Dheemanth Nagaraj
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0833 , G06F12/0817 , G06F12/0822 , G06F12/0831 , G06F12/084 , G06F13/4265 , G06F2212/621 , G06F2212/622
摘要： In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，确定与存储器位置相关联的目录条目是否指示该信息不存在于远程高速缓存代理中，如果是，则将该信息从存储器关于读取请求的窥探处理之前的第一高速缓存代理的位置被完成。描述和要求保护其他实施例。

4. 发明授权

US08656115B2 Extending a cache coherency snoop broadcast protocol with directory information 失效
公开(公告)号：US08656115B2
公开(公告)日：2014-02-18
申请号：US12860340
申请日：2010-08-20
申请人： Sailesh Kottapalli , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Dheemanth Nagaraj
发明人： Sailesh Kottapalli , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Dheemanth Nagaraj
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0833 , G06F12/0817 , G06F12/0822 , G06F12/0831 , G06F12/084 , G06F13/4265 , G06F2212/621 , G06F2212/622
摘要： In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.

5. 发明申请

US20220014202A1 Three-Dimensional Stacked Programmable Logic Fabric and Processor Design Architecture 有权
公开(公告)号：US20220014202A1
公开(公告)日：2022-01-13
申请号：US17485119
申请日：2021-09-24
申请人： Rahul Pal , Dheeraj Subbareddy , Mahesh Kumashikar , Dheemanth Nagaraj , Rajesh Vivekanandham , Anshuman Thakur , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
发明人： Rahul Pal , Dheeraj Subbareddy , Mahesh Kumashikar , Dheemanth Nagaraj , Rajesh Vivekanandham , Anshuman Thakur , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari
IPC分类号： H03K19/17796 , G06F15/78 , G06F30/34 , H03K19/17758
摘要： The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.

6. 发明授权

US08799586B2 Memory mirroring and migration at home agent 有权
标题翻译：内部镜像和迁移在本地代理
公开(公告)号：US08799586B2
公开(公告)日：2014-08-05
申请号：US12571382
申请日：2009-09-30
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric Delano , Gregory S. Averill
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0817
摘要： Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.
摘要翻译：描述了与归属代理（HA）的内存镜像和迁移有关的方法和设备。在一个实施例中，归属代理可以在从属代理处镜像其数据。在一些实施例中，目录中的位可以指示高速缓存行的状态。还公开了其他实施例。

7. 发明授权

US08782347B2 Controllably exiting an unknown state of a cache coherency directory 有权
标题翻译：可控退出高速缓存一致性目录的未知状态
公开(公告)号：US08782347B2
公开(公告)日：2014-07-15
申请号：US12492280
申请日：2009-06-26
申请人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric DeLano , Gregory S. Averill
发明人： Ganesh Kumar , Dheemanth Nagaraj , Vincent R. Freytag , Eric DeLano , Gregory S. Averill
IPC分类号： G06F13/28 , G06F12/08 , G06F9/50
CPC分类号： G06F12/0817 , G06F9/5033 , G06F2212/1032
摘要： In one embodiment, a method includes receiving a read request from a first caching agent and if a directory entry associated with the request is in an unknown state, an invalidating snoop message is sent to at least one other caching agent to invalidate information in a cache location of the other caching agent corresponding to the location of the read request, to enable setting of the directory entry into a known state. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，并且如果与请求相关联的目录条目处于未知状态，则向至少一个其他高速缓存代理发送无效侦听消息以使高速缓存中的信息无效与读取请求的位置相对应的其他高速缓存代理的位置，以使目录项进入已知状态。描述和要求保护其他实施例。

8. 发明授权

US08473791B2 Redundant memory to mask DRAM failures 有权
标题翻译：冗余内存来屏蔽DRAM故障
公开(公告)号：US08473791B2
公开(公告)日：2013-06-25
申请号：US11742446
申请日：2007-04-30
申请人： Mark Shaw , Larry Thayer , Chris Petersen , Lidia Warnes , Dheemanth Nagaraj
发明人： Mark Shaw , Larry Thayer , Chris Petersen , Lidia Warnes , Dheemanth Nagaraj
IPC分类号： G11C29/00
CPC分类号： G06F11/1666 , G06F11/20 , G11C11/401 , G11C29/76 , G11C29/816
摘要： A method comprises detecting a defective area in a Dynamic Random Access Memory (DRAM). The method further comprises establishing a redundant memory buffer at a per-memory module level. The method still further comprises loading the redundant memory buffer with a copy of data from the defective area. The method additionally comprises substituting data from the redundant memory buffer for data stored in the defective area upon a memory access to the defective area.
摘要翻译：一种方法包括检测动态随机存取存储器（DRAM）中的缺陷区域。该方法还包括在每存储器模块级别建立冗余存储器缓冲器。该方法还包括从冗余存储器缓冲器加载来自缺陷区域的数据副本。该方法还包括在存储器访问缺陷区域时从冗余存储缓冲器中取代存储在缺陷区域中的数据的数据。

9. 发明申请

US20080270826A1 REDUNDANT MEMORY TO MASK DRAM FAILURES 有权
标题翻译：冗长的记忆，以掩盖DRAM故障
公开(公告)号：US20080270826A1
公开(公告)日：2008-10-30
申请号：US11742446
申请日：2007-04-30
申请人： Mark SHAW , Larry Thayer , Chris Petersen , Lidia Warnes , Dheemanth Nagaraj
发明人： Mark SHAW , Larry Thayer , Chris Petersen , Lidia Warnes , Dheemanth Nagaraj
IPC分类号： G06F11/00
CPC分类号： G06F11/1666 , G06F11/20 , G11C11/401 , G11C29/76 , G11C29/816
摘要： A method comprises detecting a defective area in a Dynamic Random Access Memory (DRAM). The method further comprises establishing a redundant memory buffer at a per-memory module level. The method still further comprises loading the redundant memory buffer with a copy of data from the defective area. The method additionally comprises substituting data from the redundant memory buffer for data stored in the defective area upon a memory access to the defective area.
摘要翻译：一种方法包括检测动态随机存取存储器（DRAM）中的缺陷区域。该方法还包括在每存储器模块级别建立冗余存储器缓冲器。该方法还包括从冗余存储器缓冲器加载来自缺陷区域的数据副本。该方法还包括在存储器访问缺陷区域时从冗余存储缓冲器中取代存储在缺陷区域中的数据的数据。

10. 发明申请

US20080270675A1 DEFECT MANAGEMENT FOR A SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：半导体存储系统的缺陷管理
公开(公告)号：US20080270675A1
公开(公告)日：2008-10-30
申请号：US11740052
申请日：2007-04-25
申请人： Dheemanth Nagaraj , Larry J. Thayer
发明人： Dheemanth Nagaraj , Larry J. Thayer
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： A method is provided for managing defects in a semiconductor memory system having a plurality of addressable locations. In the method, a first plurality of the addressable locations is allocated as in-use locations, and a second plurality of the addressable locations is allocated as spare locations. A plurality of sets of the in-use locations, wherein each of the sets is associated with a memory defect, is determined. At least one of the sets includes a different number of in-use locations than another of the sets. Each of the sets of the in-use locations is associated with at least one corresponding set of the spare locations. Each of a plurality of data requests that is associated with one of the sets of the in-use locations is directed to the at least one corresponding set of the spare locations.
摘要翻译：提供一种用于管理具有多个可寻址位置的半导体存储器系统中的缺陷的方法。在该方法中，第一多个可寻址位置被分配为使用中的位置，并且第二多个可寻址位置被分配为备用位置。确定其中每个组与存储器缺陷相关联的多组使用中的位置。这些组中的至少一个包括不同数量的使用位置，而不是另外一组。每个使用中的位置集合与至少一个对应的备用位置组相关联。与正在使用的位置中的一组相关联的多个数据请求中的每一个被引导到至少一个对应的备用位置集合。

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