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1. 发明授权

US09378788B2 Negative bitline write assist circuit and method for operating the same 有权
标题翻译：负位线写辅助电路及其操作方法
公开(公告)号：US09378788B2
公开(公告)日：2016-06-28
申请号：US13997591
申请日：2012-03-15
申请人： Pramod Kolar , John Riley , Gunjan Pandya
发明人： Pramod Kolar , John Riley , Gunjan Pandya
IPC分类号： G11C7/12 , G11C7/10
CPC分类号： G11C7/12 , G11C7/10 , G11C7/1096 , G11C7/22
摘要： A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.
摘要翻译：负位线写入辅助电路包括被配置为有助于驱动位线的电容的偏置电容器。负位线写辅助电路可以在电路内模块化复制，以在写操作期间改变位线上的负电压量。位线写辅助电路可以直接耦合到位线，从而不需要向写驱动器添加下拉晶体管。

2. 发明申请

US20140169077A1 OPERATION AWARE AUTO-FEEDBACK SRAM 有权
标题翻译：操作注意自动反馈SRAM
公开(公告)号：US20140169077A1
公开(公告)日：2014-06-19
申请号：US13991423
申请日：2011-12-31
申请人： Pramod Kolar , Eric A. Karl
发明人： Pramod Kolar , Eric A. Karl
IPC分类号： G11C11/412 , G11C11/419
CPC分类号： G11C11/412 , G11C11/419
摘要： A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.
摘要翻译：描述了静态随机存取存储器。 SRAM包括存储单元和电压源，以在写入操作期间向存储单元提供降低的电压。 SRAM单元包括第一通道栅极和第二栅极。第一电阻器耦合在第一通道栅极和存储单元的第一侧之间。第二电阻器耦合在第二通道栅极和存储单元的第二侧之间。

3. 发明授权

US08451670B2 Adaptive and dynamic stability enhancement for memories 有权
标题翻译：存储器的自适应和动态稳定性增强
公开(公告)号：US08451670B2
公开(公告)日：2013-05-28
申请号：US12888575
申请日：2010-09-23
申请人： Pramod Kolar , Fatih Hamzaoglu , Yih Wang , Eric A Karl , Yong-Gee Ng , Uddalak Bhattacharya , Kevin X. Zhang , Hyunwoo Nho
发明人： Pramod Kolar , Fatih Hamzaoglu , Yih Wang , Eric A Karl , Yong-Gee Ng , Uddalak Bhattacharya , Kevin X. Zhang , Hyunwoo Nho
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C11/41 , G11C29/028
摘要： Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.
摘要翻译：描述了存储器的自适应和动态稳定性增强。在一个示例中，增强包括多个传感器，每个传感器各自位于多个存储器单元附近以提供传感器电压，控制器接收传感器电压并基于此提供控制信号;以及读/写辅助电路，耦合到控制器，用于响应于所述控制信号调整应用于对所述多个存储器单元的存储单元的读取和写入的参数。

4. 发明授权

US11521514B2 Refreshable braille display 有权
公开(公告)号：US11521514B2
公开(公告)日：2022-12-06
申请号：US17240744
申请日：2021-04-26
申请人： Prithu Kolar , Pramod Kolar
发明人： Prithu Kolar , Pramod Kolar
IPC分类号： G09B21/00
摘要： A refreshable braille display device is provided comprising a plurality of Braille pins running through a perforated body of the reader, the pins arranged in the spacing and order of Braille dots of standard Braille cells. The Braille reader may be coupled to a device for Braille text generation via selective hammering or impacting of Braille pins. From a default position where all pins of the reader are raised relative to a first, front surface of the reader, one or more pins are selectively impacted in a sequence to create a Braille pattern of raised and lowered pins based on a desired text conversion.

5. 发明申请

US20210366309A1 REFRESHABLE BRAILLE DISPLAY 有权
公开(公告)号：US20210366309A1
公开(公告)日：2021-11-25
申请号：US17240744
申请日：2021-04-26
申请人： PRITHU KOLAR , Pramod Kolar
发明人： PRITHU KOLAR , Pramod Kolar
IPC分类号： G09B21/00
摘要： A refreshable braille display device is provided comprising a plurality of Braille pins running through a perforated body of the reader, the pins arranged in the spacing and order of Braille dots of standard Braille cells. The Braille reader may be coupled to a device for Braille text generation via selective hammering or impacting of Braille pins. From a default position where all pins of the reader are raised relative to a first, front surface of the reader, one or more pins are selectively impacted in a sequence to create a Braille pattern of raised and lowered pins based on a desired text conversion.

6. 发明申请

US20140269019A1 DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM) 有权
标题翻译：双端口静态随机存取存储器（SRAM）
公开(公告)号：US20140269019A1
公开(公告)日：2014-09-18
申请号：US13842086
申请日：2013-03-15
申请人： Pramod Kolar , Gunjan H. Pandya , Uddalak Bhattacharya , Zheng Guo
发明人： Pramod Kolar , Gunjan H. Pandya , Uddalak Bhattacharya , Zheng Guo
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C8/16 , G11C11/412
摘要： In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.
摘要翻译：在一个实施例中，用于存储数据的存储单元电路包括一对交叉耦合的反相器，用于存储存储单元电路的状态。接入设备提供对一对交叉耦合逆变器的访问。存储单元电路还包括耦合到该对交叉耦合的反相器的一组电活性p型金属氧化物半导体（PMOS）器件。与一对交叉耦合的反相器的一部分（例如，PMOS器件）组合的一组非活性PMOS器件使得能够存储单元电路的连续p型扩散层。

7. 发明申请

US20140169106A1 NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE SAME 有权
标题翻译：负号位线写入辅助电路及其操作方法
公开(公告)号：US20140169106A1
公开(公告)日：2014-06-19
申请号：US13997591
申请日：2012-03-15
申请人： Pramod Kolar , John Riley , Gunjan Pandya
发明人： Pramod Kolar , John Riley , Gunjan Pandya
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/10 , G11C7/1096 , G11C7/22
摘要： A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.
摘要翻译：负位线写入辅助电路包括被配置为有助于驱动位线的电容的偏置电容器。负位线写辅助电路可以在电路内模块化复制，以在写操作期间改变位线上的负电压量。位线写辅助电路可以直接耦合到位线，从而不需要向写驱动器添加下拉晶体管。

8. 发明授权

US07286389B2 Low-power, p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells 失效
标题翻译：低功率，p沟道增强型金属氧化物半导体场效应晶体管（PMOSFET）SRAM单元
公开(公告)号：US07286389B2
公开(公告)日：2007-10-23
申请号：US11186395
申请日：2005-07-21
申请人： Pramod Kolar , Hisham Z. Massoud
发明人： Pramod Kolar , Hisham Z. Massoud
IPC分类号： G11C11/412
CPC分类号： G11C11/412 , Y10S257/903
摘要： Low-power, all-p-channel enhancement-type metal-oxide semiconductor field-effect transistor (PMOSFET) SRAM cells are disclosed. A PMOSFET SRAM cell is disclosed. The SRAM cell can include a latch having first and second PMOSFETs for storing data. Further, a gate of the first PMOSFET is connected to a drain of the second PMOSFET at a first memory node. A gate of the second PMOSFET is connected to a drain of the first PMOSFET at a second memory node. The SRAM cell can also include third and fourth PMOSFETs forming a pull-down circuit. A source of the third PMOSFET is connected to the first memory node. Further, a source of the fourth PMOSFET is connected to the second memory node. The SRAM cell can include access circuitry for accessing data at the first and second memory nodes for read or write operations.
摘要翻译：公开了低功率，全P沟道增强型金属氧化物半导体场效应晶体管（PMOSFET）SRAM单元。公开了PMOSFET SRAM单元。 SRAM单元可以包括具有用于存储数据的第一和第二PMOSFET的锁存器。此外，第一PMOSFET的栅极在第一存储器节点处连接到第二PMOSFET的漏极。第二PMOSFET的栅极在第二存储器节点处连接到第一PMOSFET的漏极。 SRAM单元还可以包括形成下拉电路的第三和第四PMOSFET。第三PMOSFET的源极连接到第一存储器节点。此外，第四PMOSFET的源极连接到第二存储器节点。 SRAM单元可以包括用于访问第一和第二存储器节点处的数据以进行读取或写入操作的访问电路。

9. 发明授权

US09767890B2 Operation aware auto-feedback SRAM 有权
公开(公告)号：US09767890B2
公开(公告)日：2017-09-19
申请号：US13991423
申请日：2011-12-31
申请人： Pramod Kolar , Eric A. Karl
发明人： Pramod Kolar , Eric A. Karl
IPC分类号： G11C11/412 , G11C11/419
CPC分类号： G11C11/412 , G11C11/419
摘要： A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.

10. 发明申请

US20120075938A1 Adaptive and Dynamic Stability Enhancement for Memories 有权
标题翻译：记忆的自适应和动态稳定性增强
公开(公告)号：US20120075938A1
公开(公告)日：2012-03-29
申请号：US12888575
申请日：2010-09-23
申请人： Pramod Kolar , Fatih Hamzaoglu , Yih Wang , Eric A. Karl , Yong-Gee NG , Uddalak Bhattacharya , Kevin X. Zhang , Hyunwoo Nho
发明人： Pramod Kolar , Fatih Hamzaoglu , Yih Wang , Eric A. Karl , Yong-Gee NG , Uddalak Bhattacharya , Kevin X. Zhang , Hyunwoo Nho
IPC分类号： G11C8/08 , G11C7/00
CPC分类号： G11C11/419 , G11C11/41 , G11C29/028
摘要： Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.
摘要翻译：描述了存储器的自适应和动态稳定性增强。在一个示例中，增强包括多个传感器，每个传感器各自位于多个存储器单元附近以提供传感器电压，控制器接收传感器电压并基于此提供控制信号;以及读/写辅助电路，耦合到控制器，以响应于所述控制信号来调整应用于对所述多个存储器单元的存储单元的读取和写入的参数。

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