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1. 发明授权

US07474612B1 Multi-function bypass port and port bypass circuit 有权
标题翻译：多功能旁路端口和端口旁路电路
公开(公告)号：US07474612B1
公开(公告)日：2009-01-06
申请号：US10805441
申请日：2004-03-22
申请人： Bijit T. Patel
发明人： Bijit T. Patel
IPC分类号： H04J1/16 , H04J3/06
CPC分类号： H04J3/062 , H04J3/0685
摘要： An architecture is provided for implementing bypass, repeater and retimer functions in high-speed multi-port SERDES bypass ports and devices. Specifically, this architecture uses clock recovery to implement a repeater function which retransmits data synchronously at a recovered-clock rate, providing very low-latency as no elastic-buffers are required to perform clock-rate compensation. It also supports a full retiming function where incoming data is retransmitted synchronously to the local-clock domain, in which case elastic-buffers are needed to compensate for differences between incoming clock and local-clock domains. The architecture disclosed herein is advantageously used for Fibre-Channel Arbitrated Loop (FCAL) applications. It can also be leveraged in other applications like Infiniband, XAUI, PCI-Express to create a single device that be used as “eye-opener” to extend reach with low-latency when operated in “repeater mode” and as retiming device when operated as “retimer-mode”. It can also perform as an amplifier with very low-latency when operated in bypass-mode.
摘要翻译：提供了一种用于在高速多端口SERDES旁路端口和设备中实现旁路，中继器和重定时器功能的架构。具体来说，该架构使用时钟恢复来实现以恢复时钟速率同步重传数据的中继器功能，提供非常低的延迟，因为不需要弹性缓冲器来执行时钟速率补偿。它还支持完全重定时功能，其中输入数据与本地时钟域同步重传，在这种情况下需要弹性缓冲器来补偿输入时钟和本地时钟域之间的差异。本文公开的架构有利地用于光纤通道仲裁环（FCAL）应用。它还可以在其他应用程序（如Infiniband，XAUI，PCI-Express）中使用，以创建一个单一的设备，在“中继器模式”下运行时，作为重新启动设备运行时用作“开眼门” 作为“retimer-mode”。在旁路模式下，它也可以作为具有非常低延迟的放大器来执行。

2. 发明授权

US6094735A Speed-signaling testing for integrated circuits 有权
标题翻译：集成电路的速度信号测试
公开(公告)号：US6094735A
公开(公告)日：2000-07-25
申请号：US128041
申请日：1998-08-03
申请人： Clifford B. Cole , Joseph D. Coyne , Bijit T. Patel , Michael Shinkarovsky
发明人： Clifford B. Cole , Joseph D. Coyne , Bijit T. Patel , Michael Shinkarovsky
IPC分类号： G06F11/22 , G01R31/28 , G01R31/30 , G01R31/317
CPC分类号： G01R31/3016
摘要： An integrated circuit has digital logic that supports two or more different processing speeds and two or more different data rates that are distinguished by each data rate having a data prefix at a different common-mode voltage. For normal processing, the integrated circuit has one or more comparators that compare the average signal voltage level with one or more reference voltages to determine the data rate. According to one embodiment of the invention, one or more muxes are configured between the comparators and the digital logic. These muxes can be controlled during testing to by-pass the operations of the comparators to pass specified digital codes to the digital logic to simulate the operations of the comparators. In this way, the different processing speeds of the digital logic can be tested without having to build special automatic test equipment to support all of the different possible voltage levels corresponding to the different supported data rates.
摘要翻译：集成电路具有数字逻辑，其支持两种或多种不同的处理速度和两种或更多种不同的数据速率，每种数据速率由具有不同共模电压的数据前缀的每个数据速率区分。对于正常处理，集成电路具有一个或多个比较器，其将平均信号电压电平与一个或多个参考电压进行比较以确定数据速率。根据本发明的一个实施例，在比较器和数字逻辑之间配置一个或多个多路复用器。在测试期间可以控制这些多路复用器，以便旁路比较器的操作，以将指定的数字代码传递给数字逻辑以模拟比较器的操作。以这种方式，可以测试数字逻辑的不同处理速度，而无需构建特殊的自动测试设备来支持与不同支持的数据速率对应的所有不同的可能电压电平。

3. 发明授权

US6087853A Controlled output impedance buffer using CMOS technology 失效
标题翻译：使用CMOS技术的受控输出阻抗缓冲器
公开(公告)号：US6087853A
公开(公告)日：2000-07-11
申请号：US100939
申请日：1998-06-22
申请人： Carol A. Huber , Bernard L. Morris , Bijit T. Patel
发明人： Carol A. Huber , Bernard L. Morris , Bijit T. Patel
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K19/0005
摘要： CMOS technology is used to create a controlled output impedance output buffer circuit. An output buffer driver uses buffer circuits having impedance elements with linear characteristics. A control circuit uses a known impedance load to control the impedance of the buffer circuits. The control circuit monitors a known current flowing through the known impedance load to determine whether the output buffer circuit's output impedance needs to be adjusted to match a transmission line's impedance. Adjustments occur when the control circuit generates control signals to turn on or off various buffer circuits (and their impedance elements) contained within the output driver. In doing so, the output buffer circuit ensures that its output impedance will match the impedance of a transmission line over the entire range of output voltages regardless of the variations caused by the manufacturing process, operation temperature and power supply voltage.
摘要翻译： CMOS技术用于创建受控输出阻抗输出缓冲电路。输出缓冲器驱动器使用具有线性特性的阻抗元件的缓冲电路。控制电路使用已知的阻抗负载来控制缓冲电路的阻抗。控制电路监测流过已知阻抗负载的已知电流，以确定输出缓冲电路的输出阻抗是否需要调整以匹配传输线的阻抗。当控制电路产生控制信号以导通或关闭包含在输出驱动器内的各种缓冲电路（及其阻抗元件）时，发生调整。在这样做时，输出缓冲电路确保其输出阻抗将与输出电压的整个范围内的传输线的阻抗匹配，而不管制造过程，操作温度和电源电压引起的变化如何。

4. 发明授权

US5784575A Output driver that parks output before going tristate 失效
标题翻译：输出驱动器，在三态之前停放输出
公开(公告)号：US5784575A
公开(公告)日：1998-07-21
申请号：US685128
申请日：1996-07-24
申请人： Steven F. Oakland , Bijit T. Patel , Patrick E. Perry
发明人： Steven F. Oakland , Bijit T. Patel , Patrick E. Perry
IPC分类号： G06F13/40 , H03K19/094 , G06F13/00
CPC分类号： G06F13/4072 , H03K19/09429
摘要： Disclosed is a tristate circuit driver capable of both parking the output in a deasserted state and switching to a tristate mode in less than one clock cycle. In a preferred embodiment, the driver circuitry utilized a delay device to generate a pulse signal immediately after the transition in an enable signal is detected. The pulse signal then causes the tristate driver to output a signal of a predetermined voltage for a duration of less then one clock cycle.
摘要翻译：公开了一种三态电路驱动器，其能够将输出停止在无效状态并且在不到一个时钟周期内切换到三态模式。在优选实施例中，驱动器电路利用延迟器件在检测到使能信号中的转变之后立即产生脉冲信号。然后脉冲信号使三态驱动器在小于一个时钟周期的持续时间内输出预定电压的信号。

5. 发明授权

US5635861A Off chip driver circuit 失效
标题翻译：片外驱动电路
公开(公告)号：US5635861A
公开(公告)日：1997-06-03
申请号：US671045
申请日：1996-06-27
申请人： Francis Chan , Bijit T. Patel
发明人： Francis Chan , Bijit T. Patel
IPC分类号： H03K19/003 , H03K19/0948 , H03K19/0185
CPC分类号： H03K19/00315
摘要： Disclosed is an improved push-pull off-chip driver circuit. The circuit includes a push-pull amplifier including a pull-up transistor and a pull-down transistor, each provided with independent inputs and connected at the output node. The input to the pull-up transistor is provided by a transmission gate having an n-channel transistor connected in parallel with a p-channel transistor. A control transistor is coupled between the output node and the gate of the pull-up transistor to provide a protective bias. A feedback override circuit is coupled between the output node and the gate of the p-channel transmission gate transistor to selectively provide either Vout or a low level potential to that gate. The feedback override circuit improves the response time and noise immunity of a prior art off-chip driver in the active mode in a manner consistent with the objectives of protecting the gate oxides from high voltage stress and prevent leakage currents during the high-impedance mode.
摘要翻译：公开了一种改进的推挽片外驱动电路。该电路包括一个包括上拉晶体管和一个下拉晶体管的推挽放大器，每个都具有独立的输入并在输出节点连接。上拉晶体管的输入由具有与p沟道晶体管并联连接的n沟道晶体管的传输栅极提供。控制晶体管耦合在输出节点和上拉晶体管的栅极之间以提供保护偏置。反馈超控电路耦合在输出节点和p沟道传输门晶体管的栅极之间，以选择性地向该栅极提供Vout或低电平电位。反馈覆盖电路以与保护栅极氧化物免受高电压应力和防止高阻抗模式下的漏电流的目的一致的方式，改善了现有技术的芯片内驱动器在有源模式下的响应时间和抗噪声能力。

6. 发明授权

US5933027A High-voltage-tolerant output buffers in low-voltage technology 失效
标题翻译：高电压技术中的高耐压输出缓冲器
公开(公告)号：US5933027A
公开(公告)日：1999-08-03
申请号：US879212
申请日：1997-06-19
申请人： Bernard L. Morris , Bijit T. Patel
发明人： Bernard L. Morris , Bijit T. Patel
IPC分类号： H01L27/04 , H01L21/822 , H03K19/003 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/00315
摘要： An integrated circuit is implemented in a low-voltage technology and has an output driver. The output driver has circuitry adapted to generate an output voltage at an output node (e.g., PAD in FIG. 1) based on an input voltage (e.g., A). Within the output driver, a transistor is configured to limit the drain-to-source voltage drop across another transistor to enable the integrated circuit to tolerate, at its output node, voltages of magnitude up to two times the operating voltage of the integrated circuit. The invention enables low-voltage integrated circuits to be interfaced with other circuitry implemented in a relatively high-voltage technology, without suffering the adverse effects that can otherwise result in the low-voltage circuitry from such interfacing.
摘要翻译：集成电路采用低压技术实现，并具有输出驱动器。输出驱动器具有适于基于输入电压（例如，A）在输出节点（例如，图1中的PAD）产生输出电压的电路。在输出驱动器内，晶体管被配置为限制跨另一晶体管的漏极 - 源极电压降，以使得集成电路在其输出节点容忍高达集成电路的工作电压的两倍的电压。本发明使得低电压集成电路能够与在相对高压技术中实现的其它电路接口，而不会产生不利影响，否则可能导致低压电路不受这种接口的影响。

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