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1. 发明申请

WO2006013524A1 TESTING OF A CIRCUIT THAT HAS AN ASYNCHRONOUS TIMING CIRCUIT 审中-公开
标题翻译：具有异步时序电路的电路的测试
公开(公告)号：WO2006013524A1
公开(公告)日：2006-02-09
申请号：PCT/IB2005/052455
申请日：2005-07-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PEETERS, Adrianus, M., G. , TE BEEST, Frank, J.
发明人： PEETERS, Adrianus, M., G. , TE BEEST, Frank, J.
IPC分类号： G01R31/3185
CPC分类号： G01R31/318533
摘要： Special test measures are required to test an asynchronous timing circuit. The asynchronous timing circuit (14) comprises a time-continuous feedback loop (22, 26) with a combinatorial logic circuit (22) with inputs for a feedback signal and a further signal, the feedback loop having positive loop gain. A test prepared circuit that contains the timing circuit is switched to a test mode. In the test mode test data through is shifted through a shift register structure (12). The further input signal of the feedback loop is controlled dependent on test data from the shift register structure (12). The time-continuous feedback loop (22, 26) is initially broken in the test mode, substituting test data from a register (31) in the shift register structure (12) for a feedback signal. Subsequently the time-continuous feedback loop is restored in the test mode after the further signal has stabilized. A test result that has been determined by the feedback loop is captured while the feedback loop is restored, for transport through the shift register structure (12). In this way no register needs to be added in the feedback loop for test purposes. As a result testability of the asynchronous timing circuit only imposes a minimum of delay.
摘要翻译：测试异步定时电路需要特殊的测试措施。异步定时电路（14）包括具有组合逻辑电路（22）的时间连续反馈回路（22,26），该组合逻辑电路具有用于反馈信号和另一信号的输入，所述反馈回路具有正回路增益。包含定时电路的测试准备电路切换到测试模式。在测试模式下，测试数据通过移位寄存器结构（12）。反馈回路的另外的输入信号根据来自移位寄存器结构（12）的测试数据来进行控制。时间连续反馈回路（22,26）在测试模式下被初始断开，代替来自移位寄存器结构（12）中的寄存器（31）的测试数据用于反馈信号。随后在进一步的信号稳定后，在测试模式下恢复时间连续反馈回路。当反馈回路恢复时，捕获由反馈回路确定的测试结果，以便通过移位寄存器结构（12）进行传输。以这种方式，为了测试目的，无需在反馈回路中添加寄存器。因此，异步定时电路的可测试性仅施加最小的延迟。

2. 发明申请

WO2005048264A1 CONTROLLING POWER CONSUMPTION PEAKS IN ELECTRONIC CIRCUITS 审中-公开
标题翻译：控制电子电路中的功耗峰值
公开(公告)号：WO2005048264A1
公开(公告)日：2005-05-26
申请号：PCT/IB2004/052275
申请日：2004-11-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PEETERS, Adrianus, M., G. , TIMMERMANS, Daniel , DE CLERCQ, Mark, N., O.
发明人： PEETERS, Adrianus, M., G. , TIMMERMANS, Daniel , DE CLERCQ, Mark, N., O.
IPC分类号： G11C7/10
CPC分类号： G06F1/3243 , G06F1/3203 , G06F1/3275 , G11C7/1006 , G11C7/1045 , G11C2207/104 , Y02D10/14 , Y02D10/152
摘要： An electronic circuit is provided that comprises a plurality of storage elements (101 - 105) arranged for storing of data elements, and a plurality of processing elements. The plurality of processing elements processes the data elements stored in the storage elements. In operation, the points in time at which respective storage elements load their data elements are mutually different in order to meet a maximum allowable value of the power consumption peaks.
摘要翻译：提供了一种电子电路，其包括被布置用于存储数据元素的多个存储元件（101-105）和多个处理元件。多个处理元件处理存储在存储元件中的数据元素。在操作中，各个存储元件加载其数据元素的时间点是相互不同的，以便满足功耗峰值的最大允许值。

3. 发明申请

WO2004001433A1 ELECTRONIC CIRCUIT WITH ASYNCHRONOUSLY OPERATING COMPONENTS 审中-公开
标题翻译：具有异步操作部件的电子电路
公开(公告)号：WO2004001433A1
公开(公告)日：2003-12-31
申请号：PCT/IB2003/002387
申请日：2003-06-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PEETERS, Adrianus, M., G.
发明人： PEETERS, Adrianus, M., G.
IPC分类号： G01R31/3185
CPC分类号： G01R31/31701 , G01R31/31858
摘要： An electronic circuit that comprises components that operate asynchronously of one another. An interface element has inputs coupled to a respective one of the components. The interface element supplies a logic output signal that is a logic function of signals at the inputs and dependent on the relative timing of the signals at the inputs. The electronic circuit is switched to a test mode, in which test input signals are applied to the electronic circuit from a test signal source. During test a difference is caused to occur between the time intervals after which the test signal source affects different ones of the signals at the inputs of the interface element. Preferably the test control circuit activates said difference in the test mode and not in the normal operating mode.
摘要翻译：包括彼此异步操作的组件的电子电路。接口元件具有耦合到相应的一个部件的输入。接口元件提供逻辑输出信号，它是输入端的信号逻辑函数，取决于输入端的信号的相对定时。电子电路切换到测试模式，其中测试输入信号从测试信号源施加到电子电路。在测试期间，在测试信号源影响界面元件的输入端的不同信号之间的时间间隔之间发生差异。优选地，测试控制电路激活测试模式中的所述差异，而不是正常操作模式。

4. 发明申请

WO2009066238A1 ASYNCHRONOUS PIPELINE CONTROLLER 审中-公开
标题翻译：异步管道控制器
公开(公告)号：WO2009066238A1
公开(公告)日：2009-05-28
申请号：PCT/IB2008/054829
申请日：2008-11-18
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MALLON, Willem, C. , PEETERS, Adrianus, M., G.
发明人： MALLON, Willem, C. , PEETERS, Adrianus, M., G.
IPC分类号： G06F7/00 , G06F5/08
CPC分类号： G06F7/00 , G06F5/08 , G06F9/3871 , G06F2207/3864
摘要： The present invention relates to an asynchronous control device (100 ) for controlling a stage of an asynchronous pipeline (10), the control device (100 ) comprising controllogic (104 ) and a non-transparent memoryelement (102 ),wherein the control logic (104 ) is adapted to receive a request signal (108), receive an acknowledgement signal (110), receive an output signal (112) from the non-transparent memory element, and generate an enable signal (114) forthe non-transparent memoryelement (102 ), wherein the non- transparent memoryelement (102 ) is adapted to receive one of the request signal (108) and the output signal from the non-transparent memory element (102) as an input signal, and receive the enable signal (114) generated by the control logic (104 ), thereby allowing for the input signalreceived by the non-transparent memoryelement (102 ) to be provided as the output signal from the non-transparent memoryelement (102 ). Byusing a non-transparent memoryelement in the control device it is possible to utilize standard cell technologies having inbuilt design-for-test technology, thus reducing the design-for-test overhead. Using less design-for-test overhead leads to a less expensive pipeline having less complex timing constraints.
摘要翻译：本发明涉及一种用于控制异步流水线（10）的级的异步控制设备（100），该控制设备（100）包括控制（104）和不透明的记忆元件（102），其中控制逻辑（ 104）适于接收请求信号（108），接收确认信号（110），从非透明存储器元件接收输出信号（112），并且生成用于非透明记忆元件（114）的使能信号（114） 102），其中所述非透明记忆元件（102）适于接收所述请求信号（108）中的一个和来自所述非透明存储元件（102）的输出信号作为输入信号，并且接收所述使能信号（114 ），从而允许由非透明记忆元件（102）接收的输入信号作为来自不透明的记忆元件（102）的输出信号提供。通过在控制设备中使用不透明的记忆元件，可以利用具有内置的测试设计技术的标准单元技术，从而减少了测试开销。使用更少的设计为测试开销导致较不昂贵的管道具有较少复杂的时序约束。

5. 发明申请

WO2006100626A2 ELECTRONIC CIRCUIT WHEREIN AN ASYNCHRONOUS DELAY IS REALIZED 审中-公开
标题翻译：异步延时实现的电子电路实现
公开(公告)号：WO2006100626A2
公开(公告)日：2006-09-28
申请号：PCT/IB2006/050805
申请日：2006-03-15
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , KESSELS, Jozef, L., W. , PEETERS, Adrianus, M., G.
发明人： KESSELS, Jozef, L., W. , PEETERS, Adrianus, M., G.
IPC分类号： H03K5/13
CPC分类号： H03K5/13 , G06F9/3869 , H03K2005/00058 , H03K2005/00247
摘要： The electronic circuit contains a basic delay circuit (14). A delay is realized by activating the same basic delay circuit (14) a plurality of times in response to a single start signal before generating a response to that start signal. A control circuit (12) receives a start signal and an outputs a response. The control circuit (12) causes a series of signals to be passed through the delay circuit (14), the series starting at a time that is time-continuously triggered by the start signal. Each successive signal in the series starts after a preceding signal has emerged from the delay circuit (12) and the series being terminated after a controlled number of more than one signal has been passed. The control circuit (12) supplies the response upon termination of the series. In one embodiment the series is realized by means of a handshake sequencing circuit (120) that generates a series of successive handshake transactions.
摘要翻译：电子电路包含基本延迟电路（14）。通过在产生对该起始信号的响应之前响应于单个起始信号激活相同的基本延迟电路（14）来实现延迟。控制电路（12）接收起始信号并输出响应。控制电路（12）使一系列信号通过延迟电路（14），该串联信号从由起始信号时间连续触发的时间开始。在从延迟电路（12）出现先前的信号之后，串联中的每个连续信号开始，并且在经过多于一个信号的受控数量之后，串联被终止。控制电路（12）在串联终止时提供响应。在一个实施例中，该系列通过产生一系列连续握手事务的握手排序电路（120）来实现。

6. 发明申请

WO2002101926A2 INTEGRATED CIRCUIT AND METHOD FOR TESTING THE INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路和测试集成电路的方法
公开(公告)号：WO2002101926A2
公开(公告)日：2002-12-19
申请号：PCT/IB2002/002206
申请日：2002-06-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN BERKEL, Cornelis, H. , PEETERS, Adrianus, M., G.
发明人： VAN BERKEL, Cornelis, H. , PEETERS, Adrianus, M., G.
IPC分类号： H03K3/037
CPC分类号： G01R31/318594 , G01R31/318541 , G01R31/318552 , H03K3/0375
摘要： An integrated circuit according to the invention comprises a plurality of units (C1, C2, C3, C4;1), having first inputs (2a, 2b, 2c) for receiving control signals (n,s,t) for setting an operational mode of the unit (1). The units (1) have a functional mode, a scan in mode, a scan out mode. In the functional mode (n=1,s=0,t=1) a logical operation is performed at signals (a,b) received at one or more second inputs (4a, 4b). The result of the logical operation is provided via an internal node (6) to an output (10). In the scan in mode (n=0,s=1,t=0) a value at a scan input is stored at the internal node (6). In the scan out mode (n=0,s=0,t=1) the value at the internal node (6) is provided to the output (10). The integrated circuit according to the invention further has an evaluate mode (n=1,s=0,t=0) in which the result of the logical operation at the input signals (a,b) is stored at the internal node (6), and in which the output (10) of the units is disabled.
摘要翻译：根据本发明的集成电路包括多个单元（C1，C2，C3，C4; 1），具有用于接收用于设置操作模式的控制信号（n，s，t）的第一输入端（2a，2b，2c）的单元（1）。单元（1）具有功能模式，扫描模式，扫描输出模式。在功能模式（n = 1，s = 0，t = 1）中，在一个或多个第二输入（4a，4b）处接收的信号（a，b）执行逻辑运算。逻辑运算的结果经由内部节点（6）提供给输出（10）。在扫描模式（n = 0，s = 1，t = 0）中，扫描输入处的值存储在内部节点（6）处。在扫描输出模式（n = 0，s = 0，t = 1）中，内部节点（6）的值被提供给输出（10）。根据本发明的集成电路还具有在输入信号（a，b）处的逻辑运算的结果存储在内部节点（6）处的评估模式（n = 1，s = 0，t = 0）），并且其中单元的输出（10）被禁用。

7. 发明申请

WO2005026927A2 ELECTRONIC CIRCUIT WITH A CHAIN OF PROCESSING ELEMENTS 审中-公开
标题翻译：具有加工元件链的电子电路
公开(公告)号：WO2005026927A2
公开(公告)日：2005-03-24
申请号：PCT/IB2004051599
申请日：2004-08-30
申请人： KONINKL PHILIPS ELECTRONICS NV , PEETERS ADRIANUS M G , VAN BERKEL CORNELIS H , DE CLERCQ MARK N O
发明人： PEETERS ADRIANUS M G , VAN BERKEL CORNELIS H , DE CLERCQ MARK N O
IPC分类号： G06F1/32 , G06F9/38 , G06F15/78
CPC分类号： G06F15/8053 , G06F1/32
摘要： A chain of processing element (l0a, 10, 10b) with a logic circuit (14) and a storage element (12) is provided. The storage elements (12) of all except a final processing element (10b) in the chain have one or more outputs coupled to the logic circuit (14) of a next processing element (10a, 10, l 0b) in the chain. A timing circuit (16) controls respective loading time points at which the storage elements (12) load data from the logic circuits (14) in respective ones of the processing elements (10a, 10, 10b). The data is loaded progressively later in processing elements (10a, 10, 10b) that successively precede one another in the chain. The time interval between successive loading time points of the final processing element (l0b) includes loading time points of loading all processing elements (l0a, 10) other than the final processing element (10).
摘要翻译：提供具有逻辑电路（14）和存储元件（12）的处理元件链（10a，10,10b）。除链中最终处理元件（10b）之外的所有存储元件（12）具有耦合到链中下一处理元件（10a，10,10b）的逻辑电路（14）的一个或多个输出。定时电路（16）控制存储元件（12）从处理元件（10a，10,10b）中的相应处理元件中的逻辑电路（14）加载数据的相应加载时间点。稍后将数据在处理元件（10a，10，10b）中连续地在链中先后加载。最终处理元件（10b）的连续加载时间点之间的时间间隔包括加载除最终处理元件（10）以外的所有处理元件（10a，10）的加载时间点。

8. 发明申请

WO2004001433A9 ELECTRONIC CIRCUIT WITH ASYNCHRONOUSLY OPERATING COMPONENTS 审中-公开
标题翻译：具有异步操作部件的电子电路
公开(公告)号：WO2004001433A9
公开(公告)日：2004-12-23
申请号：PCT/IB0302387
申请日：2003-06-05
申请人： KONINKL PHILIPS ELECTRONICS NV , PEETERS ADRIANUS M G
发明人： PEETERS ADRIANUS M G
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , H01L21/822 , H01L27/04 , H03K19/00
CPC分类号： G01R31/31701 , G01R31/31858
摘要： An electronic circuit that comprises components that operate asynchronously of one another. An interface element has inputs coupled to a respective one of the components. The interface element supplies a logic output signal that is a logic function of signals at the inputs and dependent on the relative timing of the signals at the inputs. The electronic circuit is switched to a test mode, in which test input signals are applied to the electronic circuit from a test signal source. During test a difference is caused to occur between the time intervals after which the test signal source affects different ones of the signals at the inputs of the interface element. Preferably the test control circuit activates said difference in the test mode and not in the normal operating mode.
摘要翻译：包括彼此异步操作的组件的电子电路。接口元件具有耦合到相应的一个部件的输入。接口元件提供逻辑输出信号，该信号是输入端的信号的逻辑功能，取决于输入端的信号的相对定时。电子电路切换到测试模式，其中测试输入信号从测试信号源施加到电子电路。在测试期间，在测试信号源影响界面元件的输入端的不同信号之间的时间间隔之间发生差异。优选地，测试控制电路激活测试模式中的所述差异，而不是正常操作模式。

9. 发明申请

WO2006100626A3 ELECTRONIC CIRCUIT WHEREIN AN ASYNCHRONOUS DELAY IS REALIZED 审中-公开
标题翻译：异步延时实现的电子电路实现
公开(公告)号：WO2006100626A3
公开(公告)日：2007-08-30
申请号：PCT/IB2006050805
申请日：2006-03-15
申请人： KONINKL PHILIPS ELECTRONICS NV , KESSELS JOZEF L W , PEETERS ADRIANUS M G
发明人： KESSELS JOZEF L W , PEETERS ADRIANUS M G
IPC分类号： H03K5/13
CPC分类号： H03K5/13 , G06F9/3869 , H03K2005/00058 , H03K2005/00247
摘要： The electronic circuit contains a basic delay circuit (14). A delay is realized by activating the same basic delay circuit (14) a plurality of times in response to a single start signal before generating a response to that start signal. A control circuit (12) receives a start signal and an outputs a response. The control circuit (12) causes a series of signals to be passed through the delay circuit (14), the series starting at a time that is time-continuously triggered by the start signal. Each successive signal in the series starts after a preceding signal has emerged from the delay circuit (12) and the series being terminated after a controlled number of more than one signal has been passed. The control circuit (12) supplies the response upon termination of the series. In one embodiment the series is realized by means of a handshake sequencing circuit (120) that generates a series of successive handshake transactions.
摘要翻译：电子电路包含基本延迟电路（14）。通过在产生对该起始信号的响应之前响应于单个起始信号激活相同的基本延迟电路（14）来实现延迟。控制电路（12）接收起始信号并输出响应。控制电路（12）使一系列信号通过延迟电路（14），该串联信号从由起始信号时间连续触发的时间开始。在从延迟电路（12）出现先前的信号之后，串联中的每个连续信号开始，并且在经过多于一个信号的受控数量之后，串联被终止。控制电路（12）在串联终止时提供响应。在一个实施例中，该系列通过产生一系列连续握手事务的握手排序电路（120）来实现。

10. 发明申请

WO2004066142A3 PIPELINE SYNCHRONISATION DEVICE AND METHOD 审中-公开
标题翻译：管道同步装置和方法
公开(公告)号：WO2004066142A3
公开(公告)日：2006-03-09
申请号：PCT/IB2004050024
申请日：2004-01-14
申请人： KONINKL PHILIPS ELECTRONICS NV , KESSELS JOZEF L W , PEETERS ADRIANUS M G , KIM SUK J
发明人： KESSELS JOZEF L W , PEETERS ADRIANUS M G , KIM SUK J
IPC分类号： G06F9/38 , H04L7/02
CPC分类号： G06F9/3869 , H04L7/02
摘要： Pipeline synchronisation device for transferring data between clocked devices having different clock frequencies. The Pipeline synchronisation device comprises a mousetrap buffer for exchanging data with one of said external devices said mousetrap buffer having a signalling output for coordinating the data exchange with the external device. The pipeline synchronisation device comprises further a synchroniser adapted to synchronising the change in a signalling output with the clock of the external device.
摘要翻译：用于在具有不同时钟频率的时钟设备之间传送数据的流水线同步装置。管道同步装置包括用于与所述外部设备之一交换数据的捕鼠器缓冲器，所述鼠标捕捉缓冲器具有用于协调与外部设备的数据交换的信令输出。流水线同步装置还包括一个同步器，适于使信令输出的变化与外部设备的时钟同步。

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