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1. 发明申请

WO2004029796A2 PROCESSING APPARATUS, PROCESSING METHOD AND COMPILER 审中-公开
标题翻译：加工设备，加工方法和编译器
公开(公告)号：WO2004029796A2
公开(公告)日：2004-04-08
申请号：PCT/IB0303561
申请日：2003-08-08
申请人： KONINKL PHILIPS ELECTRONICS NV , LEIJTEN JEROEN A J , MALLON WILLEM C
发明人： LEIJTEN JEROEN A J , MALLON WILLEM C
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38 , G06F9/45
CPC分类号： G06F9/3016 , G06F9/30149 , G06F9/30167 , G06F9/30178 , G06F9/3836 , G06F9/3853
摘要： Differences in encoding efficiency of instructions may arise if certain operations require very large immediate values as operands, as opposed to others requiring no immediate values or small immediate values. The present invention describes a processing apparatus, a compiler as well as a method for processing data, allowing the use of instructions that require large immediate data, while simultaneously maintaining an efficient encoding and decoding of instructions. The processing apparatus comprises a plurality of issue slots (UC0, UC1, UC2, UC3), wherein each issue slot comprises a plurality of functional units (FU20, FU21, FU22). The processing apparatus is arranged for processing data, based on control signals generated from a set of instructions being executed in parallel. The processing apparatus further comprises a dedicated issue slot (UC4) arranged for loading an immediate value (IMV1) in dependence upon a dedicated instruction (IMM). The immediate value (IMV1) can be stored in a dedicated register file (RF2) and the issue slot requiring this value can retrieve it from the dedicated register file (RF2).
摘要翻译：如果某些操作需要非常大的即时值作为操作数，则可能会导致指令编码效率的差异，而不需要立即值或小的即时值的其他操作数。本发明描述了一种处理装置，编译器以及用于处理数据的方法，允许使用需要大的立即数的指令，同时保持指令的有效编码和解码。处理装置包括多个发行时隙（UC0，UC1，UC2，UC3），其中每个发行时隙包括多个功能单元（FU20，FU21，FU22）。处理装置被设置为基于从并行执行的一组指令生成的控制信号来处理数据。处理装置还包括专用发行时隙（UC4），其被设置用于根据专用指令（IMM）加载即时值（IMV1）。即时值（IMV1）可以存储在专用寄存器文件（RF2）中，需要此值的发行时隙可以从专用寄存器文件（RF2）中检索。

2. 发明申请

WO2009066238A1 ASYNCHRONOUS PIPELINE CONTROLLER 审中-公开
标题翻译：异步管道控制器
公开(公告)号：WO2009066238A1
公开(公告)日：2009-05-28
申请号：PCT/IB2008/054829
申请日：2008-11-18
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MALLON, Willem, C. , PEETERS, Adrianus, M., G.
发明人： MALLON, Willem, C. , PEETERS, Adrianus, M., G.
IPC分类号： G06F7/00 , G06F5/08
CPC分类号： G06F7/00 , G06F5/08 , G06F9/3871 , G06F2207/3864
摘要： The present invention relates to an asynchronous control device (100 ) for controlling a stage of an asynchronous pipeline (10), the control device (100 ) comprising controllogic (104 ) and a non-transparent memoryelement (102 ),wherein the control logic (104 ) is adapted to receive a request signal (108), receive an acknowledgement signal (110), receive an output signal (112) from the non-transparent memory element, and generate an enable signal (114) forthe non-transparent memoryelement (102 ), wherein the non- transparent memoryelement (102 ) is adapted to receive one of the request signal (108) and the output signal from the non-transparent memory element (102) as an input signal, and receive the enable signal (114) generated by the control logic (104 ), thereby allowing for the input signalreceived by the non-transparent memoryelement (102 ) to be provided as the output signal from the non-transparent memoryelement (102 ). Byusing a non-transparent memoryelement in the control device it is possible to utilize standard cell technologies having inbuilt design-for-test technology, thus reducing the design-for-test overhead. Using less design-for-test overhead leads to a less expensive pipeline having less complex timing constraints.
摘要翻译：本发明涉及一种用于控制异步流水线（10）的级的异步控制设备（100），该控制设备（100）包括控制（104）和不透明的记忆元件（102），其中控制逻辑（ 104）适于接收请求信号（108），接收确认信号（110），从非透明存储器元件接收输出信号（112），并且生成用于非透明记忆元件（114）的使能信号（114） 102），其中所述非透明记忆元件（102）适于接收所述请求信号（108）中的一个和来自所述非透明存储元件（102）的输出信号作为输入信号，并且接收所述使能信号（114 ），从而允许由非透明记忆元件（102）接收的输入信号作为来自不透明的记忆元件（102）的输出信号提供。通过在控制设备中使用不透明的记忆元件，可以利用具有内置的测试设计技术的标准单元技术，从而减少了测试开销。使用更少的设计为测试开销导致较不昂贵的管道具有较少复杂的时序约束。

3. 发明申请

WO2004059464A3 PROCESSING SYSTEM 审中-公开
标题翻译：加工系统
公开(公告)号：WO2004059464A3
公开(公告)日：2005-04-14
申请号：PCT/IB0305926
申请日：2003-12-04
申请人： KONINKL PHILIPS ELECTRONICS NV , PIRES DOS REIS MOREIRA ORLANDO , AUGUSTEIJN ALEXANDER , DE OLIVEIRA KASTRUP PEREIRA BE , YEDEMA WIM F D , HOOGENDIJK PAUL F , MALLON WILLEM C
发明人： PIRES DOS REIS MOREIRA ORLANDO , AUGUSTEIJN ALEXANDER , DE OLIVEIRA KASTRUP PEREIRA BE , YEDEMA WIM F D , HOOGENDIJK PAUL F , MALLON WILLEM C
IPC分类号： G06F9/00 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/3824 , G06F9/3828 , G06F9/3885 , G06F9/3891
摘要： A processing system according to the invention comprises a plurality of processing elements (PE1,...,PE7). The processing elements comprise a controller and computation means. The plurality of processing elements is dynamically reconfigurable as mutually independently operating task units (TU1, TU2, TU3), which task units comprise one processing element (PE7) or a cluster of two or more processing elements (PE3, PE4, PE5, PE6). The processing elements within a cluster are arranged to execute instructions under a common thread of program control. In this way the processing system is capable of using the same sub-set of data-path elements to exploit instruction level parallelism or task level parallelism or a combination thereof, dependent on the application.
摘要翻译：根据本发明的处理系统包括多个处理元件（PE1，...，PE7）。处理元件包括控制器和计算装置。所述多个处理单元作为相互独立操作的任务单元（TU1，TU2，TU3）动态地可重构，该任务单元包括一个处理单元（PE7）或两个或多个处理单元（PE3，PE4，PE5，PE6）。集群内的处理元件被布置成在程序控制的共同线程下执行指令。以这种方式，处理系统能够根据应用使用相同的数据路径元素子集来利用指令级并行性或任务级并行性或其组合。

4. 发明申请

WO2004059464A2 PROCESSING SYSTEM 审中-公开
标题翻译：加工系统
公开(公告)号：WO2004059464A2
公开(公告)日：2004-07-15
申请号：PCT/IB2003/005926
申请日：2003-12-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PIRES DOS REIS MOREIRA, Orlando, M. , AUGUSTEIJN, Alexander , DE OLIVEIRA KASTRUP PEREIRA, Bernardo , YEDEMA, Wim, F., D. , HOOGENDIJK, Paul, F. , MALLON, Willem, C.
发明人： PIRES DOS REIS MOREIRA, Orlando, M. , AUGUSTEIJN, Alexander , DE OLIVEIRA KASTRUP PEREIRA, Bernardo , YEDEMA, Wim, F., D. , HOOGENDIJK, Paul, F. , MALLON, Willem, C.
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/3824 , G06F9/3828 , G06F9/3885 , G06F9/3891
摘要： A processing system according to the invention comprises a plurality of processing elements (PE1,...,PE7). The processing elements comprise a controller and computation means. The plurality of processing elements is dynamically reconfigurable as mutually independently operating task units (TU1, TU2, TU3), which task units comprise one processing element (PE7) or a cluster of two or more processing elements (PE3, PE4, PE5, PE6). The processing elements within a cluster are arranged to execute instructions under a common thread of program control. In this way the processing system is capable of using the same sub-set of data-path elements to exploit instruction level parallelism or task level parallelism or a combination thereof, dependent on the application.
摘要翻译：根据本发明的处理系统包括多个处理元件（PE1，...，PE7）。处理元件包括控制器和计算装置。所述多个处理单元作为相互独立操作的任务单元（TU1，TU2，TU3）动态地可重构，该任务单元包括一个处理单元（PE7）或两个或多个处理单元（PE3，PE4，PE5，PE6）。集群内的处理元件被布置成在程序控制的共同线程下执行指令。以这种方式，处理系统能够根据应用使用相同的数据路径元素子集来利用指令级并行性或任务级并行性或其组合。

5. 发明申请

WO2004029796A3 APPARATUS, METHOD ,AND COMPILER ENABLING PROCESSING OF LOAD IMMEDIATE INSTRUCTIONS IN A VERY LONG INSTRUCTION WORD PROCESSOR 审中-公开
公开(公告)号：WO2004029796A3
公开(公告)日：2004-04-08
申请号：PCT/IB2003/003561
申请日：2003-08-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , LEIJTEN, Jeroen, A., J. , MALLON, Willem, C.
发明人： LEIJTEN, Jeroen, A., J. , MALLON, Willem, C.
IPC分类号： G06F9/38
摘要： Differences in encoding efficiency of instructions may arise if certain operations require very large immediate values as operands, as opposed to others requiring no immediate values or small immediate values. The present invention describes a processing apparatus, a compiler as well as a method for processing data, allowing the use of instructions that require large immediate data, while simultaneously maintaining an efficient encoding and decoding of instructions. The processing apparatus comprises a plurality of issue slots (UC0, UC1, UC2, UC3), wherein each issue slot comprises a plurality of functional units (FU20, FU21, FU22). The processing apparatus is arranged for processing data, based on control signals generated from a set of instructions being executed in parallel. The processing apparatus further comprises a dedicated issue slot (UC4) arranged for loading an immediate value (IMV1) in dependence upon a dedicated instruction (IMM). The immediate value (IMV1) can be stored in a dedicated register file (RF2) and the issue slot requiring this value can retrieve it from the dedicated register file (RF2).

6. 发明申请

WO2005060147A1 BLOCK CIPHERING SYSTEM, USING PERMUTATIONS TO HIDE THE CORE CIPHERING FUNCTION OF EACH ENCRYPTION ROUND 审中-公开
标题翻译：块式加密系统，使用PERMUTATIONS来隐藏每个加密圆的核心加密功能
公开(公告)号：WO2005060147A1
公开(公告)日：2005-06-30
申请号：PCT/IB2004/052607
申请日：2004-11-30
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , GORISSEN, Paulus, M., H., M., A. , TRESCHER, Joachim, A. , STARING, Antonius, A., M. , MALLON, Willem, C. , TREFFERS, Menno, A.
发明人： GORISSEN, Paulus, M., H., M., A. , TRESCHER, Joachim, A. , STARING, Antonius, A., M. , MALLON, Willem, C. , TREFFERS, Menno, A.
IPC分类号： H04L9/06
CPC分类号： H04L9/002 , H04L9/0625 , H04L2209/16
摘要： In a system (600), a server (610) provides a digital signal processing function ƒ to an executing device (620) in an obfuscated form. The function ƒ includes a function cascade of signal processing functions f 1 , 1 ≤ i ≤ N to formula (I). The server includes a processor (612) for selecting a set of 2 N invertible permutations p i ,, 1≤ i ≤ 2N; calculating a set of N functions g, , where g, is functionally equivalent to formula (II) for 1≤ i ≤ N ; and calculating a set of N -1 functions h, , where h, is functionally equivalent to formula (III) for 2 ≤ i ≤ N. The server includes means (614) for equipping the executing device with an execution device function cascade that includes formula (IV) , where y 1 , ... , y N are function parameters to formula (V), and means (616) for providing the functions g 1 , , ... g N to the executing device. The executing device includes means (626) for obtaining the functions g 1 ,..., g N and a processor (622) for loading the execution device function cascade and applying the loaded execution device function cascade to the functions g 1 ,...,g N (e.g.,ED,(g 1 ,...,g N )).
摘要翻译：在系统（600）中，服务器（610）以模糊形式向执行装置（620）提供数字信号处理功能f。函数f包括信号处理函数f1，1 <= I＆LE的函数级联; Nto配方（I）。服务器包括用于选择一组2N可逆排列的处理器（612），其中1 N = 计算一组N个函数g，其中g在功能上等同于1 <= i <= N的公式（II）; 并且计算一组N-1函数h，其中h在功能上等同于2 <= i <= N的公式（III）。服务器包括用于装备执行装置具有执行装置功能级联的装置（614）其包括公式（IV），其中y1，...，yN是对公式（V）的函数参数，以及用于向执行装置提供函数g1，...，gN的装置（616）。执行装置包括用于获取功能g1，...，gN的装置（626）和用于加载执行装置功能级联的处理器（622），并将加载的执行装置功能级联应用于功能g1，...，gN （例如，ED（G1，...，GN））。

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