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1. 发明申请

WO2008018004A3 ELECTRONIC DEVICE AND METHOD FOR SYNCHRONIZING A COMMUNICATION 审中-公开
标题翻译：用于同步通信的电子设备和方法
公开(公告)号：WO2008018004A3
公开(公告)日：2008-05-22
申请号：PCT/IB2007053086
申请日：2007-08-06
申请人： KONINKL PHILIPS ELECTRONICS NV , TIMMERMANS DANIEL , VAN BERKEL CORNELIS H , BINK ADRIANUS J
发明人： TIMMERMANS DANIEL , VAN BERKEL CORNELIS H , BINK ADRIANUS J
IPC分类号： G06F15/78 , H04L12/00
CPC分类号： H04L49/40 , G06F15/7825 , H04L45/00 , H04L45/60 , H04L49/109 , H04L49/1546 , Y02D10/12 , Y02D10/13
摘要： An electronic device is provided which comprises a plurality of processing units (IPl - IP6) and a flit-synchronous network-based interconnect (N) for coupling the processing units (IPl - IP6). The network-based interconnect (N) comprises at least one first and at least one second link. The at least one second link comprises N pipeline stages. The communication via the at least one second link and the N pipeline stages constitutes a word- asynchronous communication.
摘要翻译：提供了一种电子设备，其包括用于耦合处理单元（IP1-IP6）的多个处理单元（IP1-IP6）和基于快速同步的基于网络的互连（N）。基于网络的互连（N）包括至少一个第一链路和至少一个第二链路。该至少一个第二链路包括N个流水线级。经由至少一个第二链路和N个流水线级的通信构成字异步通信。

2. 发明申请

WO2008018004A2 ELECTRONIC DEVICE AND METHOD FOR SYNCHRONIZING A COMMUNICATION 审中-公开
标题翻译：电子设备和用于同步通信的方法
公开(公告)号：WO2008018004A2
公开(公告)日：2008-02-14
申请号：PCT/IB2007/053086
申请日：2007-08-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TIMMERMANS, Daniel , VAN BERKEL, Cornelis, H. , BINK, Adrianus, J.
发明人： TIMMERMANS, Daniel , VAN BERKEL, Cornelis, H. , BINK, Adrianus, J.
IPC分类号： G06F15/78 , H04L12/00
CPC分类号： H04L49/40 , G06F15/7825 , H04L45/00 , H04L45/60 , H04L49/109 , H04L49/1546 , Y02D10/12 , Y02D10/13
摘要： An electronic device is provided which comprises a plurality of processing units (IPl - IP6) and a flit-synchronous network-based interconnect (N) for coupling the processing units (IPl - IP6). The network-based interconnect (N) comprises at least one first and at least one second link. The at least one second link comprises N pipeline stages. The communication via the at least one second link and the N pipeline stages constitutes a word- asynchronous communication.
摘要翻译：提供了一种电子设备，其包括多个处理单元（IP1-IP6）和用于耦合处理单元（IP1-IP6）的基于飞行同步网络的互连（N）。基于网络的互连（N）包括至少一个第一和至少一个第二链路。所述至少一个第二链路包括N个流水线级。经由至少一个第二链路和N个流水线级的通信构成字异步通信。

3. 发明申请

WO2005013110A2 VOLTAGE SUPPLY STRUCTURE AND METHOD 审中-公开
标题翻译：电压供应结构与方法
公开(公告)号：WO2005013110A2
公开(公告)日：2005-02-10
申请号：PCT/IB2004/051300
申请日：2004-07-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TIMMERMANS, Daniel
发明人： TIMMERMANS, Daniel
IPC分类号： G06F1/26
CPC分类号： G06F1/32 , G06F17/5068
摘要： Fig. 1 c shows a logic tree l Oc comprising a plurality of logic paths 27, 29, 31, 33 connected at a root 11 c. The length of each path represents the delay of the path at a nominal supply voltage. The voltage supply structure for the logic tree l Oc is partitioned as shown in Fig. 3c, according to the delay of each logic path. For example, logic path 29 having the worst-case delay is supplied a voltage level V1, for example the nominal supply voltage. Logic paths 27 and 31, having a shorter delay, are supplied a second voltage level V2, which is lower than the first voltage level V 1. Logic path 33, having an even shorter delay, is supplied a third voltage level V3, which is lower than V2 and V 1. The voltage structure enables the voltage level and hence power consumption to be reduced without increasing the overall worst-case delay of the logic tree l Oc.
摘要翻译：图。图1c示出了逻辑树l oc，其包括以根部11c连接的多个逻辑路径27,29,31,33。每个路径的长度表示路径在标称电源电压下的延迟。逻辑树l oc的电压供应结构被分割，如图3所示。 3c，根据每个逻辑路径的延迟。例如，具有最差情况延迟的逻辑路径29被提供电压电平V1，例如标称电源电压。具有较短延迟的逻辑路径27和31被提供低于第一电压电平V 1的第二电压电平V2。具有更短延迟的逻辑路径33被提供第三电压电平V3，其是低于V2和V 1.电压结构使得能够降低电压电平并因此降低功耗，而不增加逻辑树l Oc的整体最差情况延迟。

4. 发明申请

WO2005073825A3 PROTECTION AGAINST POWER ANALYSIS ATTACKS 审中-公开
标题翻译：对电力分析攻击的保护
公开(公告)号：WO2005073825A3
公开(公告)日：2006-04-06
申请号：PCT/IB2005050254
申请日：2005-01-21
申请人： KONINKL PHILIPS ELECTRONICS NV , TIMMERMANS DANIEL
发明人： TIMMERMANS DANIEL
IPC分类号： G06F7/00 , G06F1/00 , G06F21/55
CPC分类号： G06F7/00 , G06F21/755 , G06F2207/7223 , G06F2207/7266
摘要： An electronic circuit for cryptographic processing, comprising a first combinatorial logical circuit, arranged to perform a first set of logical operations on input data and to produce output data, the output data having a functional relation to the input data, further comprising at least a second combinatorial logical circuit, arranged to perform a second set of logical operations on the same input data and to produce output data, the output data having an identical functional relation to the input data, wherein the first set of logical operations is different from the second set of logical operations, and wherein the electronic circuit is arranged to dynamically select one combinatorial logical circuit, of a set comprising at least the first combinatorial logical circuit and the second combinatorial logical circuit, for performing logical operations on the input data and producing output data.
摘要翻译：一种用于加密处理的电子电路，包括第一组合逻辑电路，被布置为对输入数据执行第一组逻辑运算并产生输出数据，所述输出数据与输入数据具有功能关系，还包括至少第二组组合逻辑电路，被布置为对相同的输入数据执行第二组逻辑运算并产生输出数据，所述输出数据与所述输入数据具有相同的功能关系，其中所述第一组逻辑运算与所述第二组不同并且其中所述电子电路被布置成动态地选择包括至少所述第一组合逻辑电路和所述第二组合逻辑电路的组的一个组合逻辑电路，以对所述输入数据执行逻辑运算并产生输出数据。

5. 发明申请

WO2005106687A1 CIRCUIT WITH ASYNCHRONOUS/SYNCHRONOUS INTERFACE 审中-公开
标题翻译：具有异步/同步接口的电路
公开(公告)号：WO2005106687A1
公开(公告)日：2005-11-10
申请号：PCT/IB2005/051360
申请日：2005-04-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TIMMERMANS, Daniel
发明人： TIMMERMANS, Daniel
IPC分类号： G06F13/40
CPC分类号： G06F13/405
摘要： Data is communicated between an asynchronously operating circuit (10) and a clocked operating sub-circuit (16, 17). A data signal is supplied from the asynchronously operating sub-circuit (10) accompanied by a blocking/non blocking control signal. A request signal from the asynchronously operating sub-circuit (10) when the data signal and the control signal are being supplied. The data is stored in response to the request at least if the control signal supplied with the data has a first value. The request signal is routed through a path through handshake elements in a handshake circuit (20, 30,40) that is arranged to generate an acknowledge signal in response to the request signal to the asynchronously operating sub-circuit (10). The path through the handshake elements dependent on the control signal, so that the acknowledge signal is generated upon storing the data signal that accompanies the request at the output into the storage element when the control signal supplied with the data has the first value, and the acknowledge signal is generated upon detecting a clock cycle of the clocked operating sub-circuit wherein the clocked operating sub-circuit accepts the data that accompanies the request when the control signal has a second value.
摘要翻译：数据在异步操作电路（10）和时钟操作子电路（16,17）之间通信。数据信号由异步操作子电路（10）提供，伴随着阻塞/非阻塞控制信号。当提供数据信号和控制信号时来自异步操作子电路（10）的请求信号。至少如果提供有数据的控制信号具有第一值，则响应于该请求存储数据。所述请求信号通过路径通过握手电路（20,30,40）中的握手元件路由，所述握手电路被布置为响应于所述异步操作子电路（10）的请求信号而产生确认信号。通过握手元件的路径取决于控制信号，使得当提供有数据的控制信号具有第一值时，在将输出中伴随请求的数据信号存储到存储元件中时产生确认信号，并且在检测到时钟操作子电路的时钟周期时产生确认信号，其中当控制信号具有第二值时，时钟操作子电路接受伴随该请求的数据。

6. 发明申请

WO2005073825A2 PROTECTION AGAINST POWER ANALYSIS ATTACKS 审中-公开
标题翻译：对电力分析攻击的保护
公开(公告)号：WO2005073825A2
公开(公告)日：2005-08-11
申请号：PCT/IB2005/050254
申请日：2005-01-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TIMMERMANS, Daniel
发明人： TIMMERMANS, Daniel
IPC分类号： G06F
CPC分类号： G06F7/00 , G06F21/755 , G06F2207/7223 , G06F2207/7266
摘要： An electronic circuit for cryptographic processing, comprising a first combinatorial logical circuit, arranged to perform a first set of logical operations on input data and to produce output data, the output data having a functional relation to the input data, further comprising at least a second combinatorial logical circuit, arranged to perform a second set of logical operations on the same input data and to produce output data, the output data having an identical functional relation to the input data, wherein the first set of logical operations is different from the second set of logical operations, and wherein the electronic circuit is arranged to dynamically select one combinatorial logical circuit, of a set comprising at least the first combinatorial logical circuit and the second combinatorial logical circuit, for performing logical operations on the input data and producing output data.
摘要翻译：一种用于加密处理的电子电路，包括第一组合逻辑电路，被布置为对输入数据执行第一组逻辑运算并产生输出数据，所述输出数据与输入数据具有功能关系，还包括至少第二组组合逻辑电路，被布置为对相同的输入数据执行第二组逻辑运算并产生输出数据，所述输出数据与所述输入数据具有相同的功能关系，其中所述第一组逻辑运算与所述第二组不同并且其中所述电子电路被布置成动态地选择包括至少所述第一组合逻辑电路和所述第二组合逻辑电路的组的一个组合逻辑电路，以对所述输入数据执行逻辑运算并产生输出数据。

7. 发明申请

WO2005013110A3 VOLTAGE SUPPLY STRUCTURE AND METHOD 审中-公开
标题翻译：电压供应结构与方法
公开(公告)号：WO2005013110A3
公开(公告)日：2005-06-16
申请号：PCT/IB2004051300
申请日：2004-07-27
申请人： KONINKL PHILIPS ELECTRONICS NV , TIMMERMANS DANIEL
发明人： TIMMERMANS DANIEL
IPC分类号： G06F1/26 , G06F1/32 , G06F17/50
CPC分类号： G06F1/32 , G06F17/5068
摘要： Fig. 1c shows a logic tree l0c comprising a plurality of logic paths (27, 29, 31, 33) connected at a root 11c. The length of each path represents the delay of the path at a nominal supply voltage. The voltage supply structure for the logic tree l0c is partitioned as shown in Fig. 3c, according to the delay of each logic path. For example, logic path (29) having the worst-case delay is supplied a voltage level V1, for example the nominal supply voltage. Logic paths (27) and (31), having a shorter delay, are supplied a second voltage level V2, which is lower than the first voltage level V1. Logic path (33), having an even shorter delay, is supplied a third voltage level V3, which is lower than V2 and V1. The voltage structure enables the voltage level and hence power consumption to be reduced without increasing the overall worst-case delay of the logic tree l0c.
摘要翻译：图。图1c示出了包括连接在根11c处的多个逻辑路径（27,29,31,33）的逻辑树l0c。每个路径的长度表示路径在标称电源电压下的延迟。逻辑树l0c的电压供应结构被分割，如图1所示。 3c，根据每个逻辑路径的延迟。例如，具有最差情况延迟的逻辑路径（29）被提供电压电平V1，例如标称电源电压。具有较短延迟的逻辑路径（27）和（31）被提供低于第一电压电平V1的第二电压电平V2。具有更短延迟的逻辑路径（33）被提供低于V2和V1的第三电压电平V3。电压结构使得能够降低电压电平并因此降低功耗，而不增加逻辑树10c的整体最差情况延迟。

8. 发明申请

WO2005069121A1 ELECTRONIC CIRCUIT WITH A FIFO PIPELINE 审中-公开
标题翻译：具有FIFO管线的电子电路
公开(公告)号：WO2005069121A1
公开(公告)日：2005-07-28
申请号：PCT/IB2004/052932
申请日：2004-12-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , TIMMERMANS, Daniel
发明人： TIMMERMANS, Daniel
IPC分类号： G06F5/06
CPC分类号： G06F5/08
摘要： An asynchronously operated FIFO pipe-line (10a-d) comprises a plurality of handshake chains functionally in parallel. Successive data items are each passed by selecting a chain dependent on a value of the data item. The FIFO pipelines (10a-d) comprise successive pipe-line stages, each pipe-line stage with respective handshake stages (12, 16) of each of the plurality of handshake chains. A coordination circuit (15) prevents handshakes in mutually different ones of handshake chains from overtaking one another. Preferably four phase handshake protocols are used with logic gates (26, 28) between the request line ((REQ1- i, REQ0- i) and the acknowledge line (ACK1- i, ACK0- i) at the input of a stage and a set-reset latch (20, 22) with a set input coupled to the output of the logic gate (26, 28). The latch has a data output coupled to the request line of at the output of the stage, a reset input coupled to the acknowledge line of the output of the stage, and a not-data output coupled to the coordination circuit (24). The coordination circuit (24) is arranged to disable response of the logic gates (26, 28) of all handshake stages in a pipeline stage while the not-data output of any one of the set-reset latches (20, 22) the pipeline stage indicates a set state.
摘要翻译：异步操作的FIFO管线（10a-d）在功能上并行地包括多个握手链。连续数据项通过选择依赖于数据项的值的链来传递。 FIFO管线（10a-d）包括连续的管线级，每个管线级具有多个握手链中的每一个的相应的握手级（12,16）。协调电路（15）防止相互不同的握手链中的握手彼此超越。优选地，在阶段的输入端处的请求线（（REQ1-i，REQ0-i）和确认线（ACK1-i，ACK0-i）之间的逻辑门（26,28）使用四相握手协议，设置复位锁存器（20,22），其具有耦合到逻辑门（26,28）的输出的设置输入，锁存器具有耦合到级输出端的请求线的数据输出，复位输入耦合所述协调电路（24）被配置为禁止所有握手级的逻辑门（26,28）的响应，所述协调电路（24）被配置为禁止所述级的输出的确认行和耦合到所述协调电路（24）在流水线级中的任何一个设置复位锁存器（20,22）的非数据输出指示流水线阶段指示设置状态。

9. 发明申请

WO2005048264A1 CONTROLLING POWER CONSUMPTION PEAKS IN ELECTRONIC CIRCUITS 审中-公开
标题翻译：控制电子电路中的功耗峰值
公开(公告)号：WO2005048264A1
公开(公告)日：2005-05-26
申请号：PCT/IB2004/052275
申请日：2004-11-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PEETERS, Adrianus, M., G. , TIMMERMANS, Daniel , DE CLERCQ, Mark, N., O.
发明人： PEETERS, Adrianus, M., G. , TIMMERMANS, Daniel , DE CLERCQ, Mark, N., O.
IPC分类号： G11C7/10
CPC分类号： G06F1/3243 , G06F1/3203 , G06F1/3275 , G11C7/1006 , G11C7/1045 , G11C2207/104 , Y02D10/14 , Y02D10/152
摘要： An electronic circuit is provided that comprises a plurality of storage elements (101 - 105) arranged for storing of data elements, and a plurality of processing elements. The plurality of processing elements processes the data elements stored in the storage elements. In operation, the points in time at which respective storage elements load their data elements are mutually different in order to meet a maximum allowable value of the power consumption peaks.
摘要翻译：提供了一种电子电路，其包括被布置用于存储数据元素的多个存储元件（101-105）和多个处理元件。多个处理元件处理存储在存储元件中的数据元素。在操作中，各个存储元件加载其数据元素的时间点是相互不同的，以便满足功耗峰值的最大允许值。

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