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1. 发明专利

CA3036879A1 INTEGRATED SOLUTION TECHNIQUES FOR SECURITY CONSTRAINED UNIT COMMITMENT PROBLEM 未知
公开(公告)号：CA3036879A1
公开(公告)日：2019-09-16
申请号：CA3036879
申请日：2019-03-15
申请人： PAN FENG , HOLZER JESSE T , CHEN YONGHONG , ROTHBERG EDWARD , VEERAMANY ARUN
发明人： PAN FENG , HOLZER JESSE T , CHEN YONGHONG , ROTHBERG EDWARD , VEERAMANY ARUN
IPC分类号： G06Q10/06 , G06F9/46 , G06Q50/06
摘要： Apparatus and methods are disclosed for solving Mixed Integer Programming (MIP) problems, such as Security Constrained Unit Commitment (SCUC) problems used by power grid authorities to perform day-ahead market clearing. In certain examples, a plurality of threads of a software tool implementing a concurrent optimizer can be executed concurrently and sequentially to generate new solutions to a SCUC problem for an upcoming planning horizon. Data can be shared among the concurrently executing threads, such as intermediate/incumbent solutions and hints regarding the fixing of variables and constraints to reduce the size of the SCUC problem. In some examples, the threads are seeded with historical solutions from prior planning horizons. The software tool can select a best solution from the solutions generated by the threads, and determine dispatch instructions for a device coupled to the power grid for the upcoming planning horizon based at least in part on the selected solution.

3. 发明专利

BRPI0408087A 未知
公开(公告)号：BRPI0408087A
公开(公告)日：2006-02-14
申请号：BRPI0408087
申请日：2004-03-03
申请人： AGENCY SCIENCE TECH & RES , PAN FENG , LIN XIAO , LIM KENG PANG , GEN NAN FENG , WU SI , RAHARDJA SUSANTO , LI ZHENG GUO , WU DA JUN , FENG GE NAN
发明人： PAN FENG , LIN XIAO , LIM KENG PANG , FENG GE NAN , WU SI , RAHARDJA SUSANTO , LI ZHENG GUO , WU DA JUN
IPC分类号： H04N7/26 , H04N19/593 , H04N7/50
摘要： A method ( 400 ) and an apparatus for AVC intra prediction to code digital video comprising a plurality of pictures are disclosed. The method comprises the steps of: generating ( 410 ) edge directional information for each intra block of a digital picture; and choosing ( 420 ) most probable intra prediction modes for rate distortion optimisation dependent upon the generated edge directional information. The edge directional information may be generated by applying at least one edge operator to the digital picture. The edge direction histogram may sum up the amplitudes of pixels with similar 15 directions in the block. The method may further comprise the step of intra coding ( 430 ) a block of the digital picture using the chosen most probable intra prediction modes.

4. 实用新型

TWM265951U 防釣竊之錢箱失效
简体标题：防钓窃之钱箱
公开(公告)号：TWM265951U
公开(公告)日：2005-06-01
申请号：TW093217862
申请日：2004-11-09
申请人：潘豐慶 PAN, FENG CHING
发明人：潘豐慶 PAN, FENG CHING
IPC分类号： A45C
摘要：一種防釣竊之錢箱，其係於錢箱之內部斜置有上、下兩隔板，兩隔板之底端均沖設有齒緣，且齒緣端係互呈不同朝向設置，可供於錢箱內部形成迂迴之通道。又齒緣皆係由數道呈直列與下斜交錯排列設置之齒條所組成，其中直列之齒條係沖壓成尖突狀，使之具有足夠之剛性，下斜之齒條則係循尖突狀齒條之側緣，向下彎折出一斜向傾角，而可具有適當之向上翹動彈性，並得於齒條間相接處形成一具斜度之叉口。藉之，而可防止由錢箱頂面投入口扔入之垂線底端直落至箱底，更得於垂線上拉時，將之予同步夾制於兩隔板之叉口內，使之無法順利自箱內拉出，兼可對之產生一愈加施力拉動，即愈形夾緊之作用，進而得將垂線予割斷，俾可有效防止錢箱內存放之香油錢遭竊者。
简体摘要：一种防钓窃之钱箱，其系于钱箱之内部斜置有上、下两隔板，两隔板之底端均冲设有齿缘，且齿缘端系互呈不同朝向设置，可供于钱箱内部形成迂回之信道。又齿缘皆系由数道呈直列与下斜交错排列设置之齿条所组成，其中直列之齿条系冲压成尖突状，使之具有足够之刚性，下斜之齿条则系循尖突状齿条之侧缘，向下弯折出一斜向倾角，而可具有适当之向上翘动弹性，并得于齿条间相接处形成一具斜度之叉口。藉之，而可防止由钱箱顶面投入口扔入之垂线底端直落至箱底，更得于垂在线拉时，将之予同步夹制于两隔板之叉口内，使之无法顺利自箱内拉出，兼可对之产生一愈加施力拉动，即愈形夹紧之作用，进而得将垂线予割断，俾可有效防止钱箱内存放之香油钱遭窃者。

5. 发明申请

WO2013138199A1 NON-VOLATILE STORAGE WITH READ PROCESS THAT REDUCES DISTURB 审中-公开
标题翻译：具有读取过程的非易失性存储，减少了干扰
公开(公告)号：WO2013138199A1
公开(公告)日：2013-09-19
申请号：PCT/US2013/029991
申请日：2013-03-08
申请人： SANDISK TECHNOLOGIES, INC. , LEI, Bo , WAN, Jun , PAN, Feng
发明人： LEI, Bo , WAN, Jun , PAN, Feng
IPC分类号： G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3427
摘要： A apparatus and process for reading data from non-volatile storage includes applying a read compare signal to a selected data memory cell of a NAND string, applying a first set of one or more read pass voltages to unselected data memory cells at both ends of the NAND string and applying a second set of one or more read pass voltages to unselected data memory cells between both ends of the NAND string and on both sides of the selected data memory cell. The second set of one or more read pass voltages are all higher than the first set of one or more read pass voltages.
摘要翻译：用于从非易失性存储器读取数据的装置和处理包括将读取的比较信号应用于NAND串的所选择的数据存储单元，将第一组一个或多个读取通过电压施加到未读选择数据存储单元的两端 NAND串，并且将第二组一个或多个读取通过电压施加到NAND串的两端和所选数据存储单元的两侧之间的未选择的数据存储单元。第一组一个或多个读通道电压都高于一个或多个读通道电压的第一组。

6. 发明申请

WO2008036609A2 IMPLEMENTATION OF OUTPUT FLOATING SCHEME FOR HV CHARGE PUMPS 审中-公开
标题翻译：高压充电泵输出浮动方案的实现
公开(公告)号：WO2008036609A2
公开(公告)日：2008-03-27
申请号：PCT/US2007/078667
申请日：2007-09-17
申请人： SANDISK CORPORATION , GOVINDU, Prashanti , PAN, Feng , MUI, Man , KWON, Gyuwan , PHAM, Trung , WANG, Chi-Ming
发明人： GOVINDU, Prashanti , PAN, Feng , MUI, Man , KWON, Gyuwan , PHAM, Trung , WANG, Chi-Ming
CPC分类号： G11C16/30 , G11C5/145
摘要： According to different embodiments of the present invention, various methods, devices and systems are described for managing power in charge pumps in a non-volatile memory system having a high voltage charge pump and associated regulator. A method includes the following operations, receiving an operation command corresponding to an operation, pumping up a charge pump output voltage to a desired output voltage, turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out, and compensating for junction leakage by turning on the regulator and the charge pump until the charge pump output voltage is the desired output voltage.
摘要翻译：根据本发明的不同实施例，描述了用于管理具有高电压电荷泵和相关联的调节器的非易失性存储器系统中的电荷泵中的功率的各种方法，设备和系统。一种方法包括以下操作：接收对应于操作的操作命令，将电荷泵输出电压上升到期望的输出电压，当输出电压近似为补偿电荷的期望输出电压时关闭调节器和电荷泵通过打开电荷泵并将泵时钟速率设置为较慢的时钟速率来共享，以避免在执行操作时通过电荷泵超出期望的输出电压，并且通过接通调节器来补偿结泄漏并且电荷泵，直到电荷泵输出电压是所需的输出电压。

7. 发明申请

WO2008024822A3 APPARATUS AND METHOD OF SYNCHRONIZING DISTRIBUTION OF PACKET SERVICES ACROSS A DISTRIBUTED NETWORK 审中-公开
公开(公告)号：WO2008024822A3
公开(公告)日：2008-02-28
申请号：PCT/US2007/076489
申请日：2007-08-22
申请人： BRILLIANT TELECOMMUNICATIONS, INC. , BARRY, Charles, F. , PARKER, Reed, A. , SHEN, Tian , PAN, Feng, F. , SUBRAMANIAN, Meenakshi, S.
发明人： BARRY, Charles, F. , PARKER, Reed, A. , SHEN, Tian , PAN, Feng, F. , SUBRAMANIAN, Meenakshi, S.
IPC分类号： H04J3/06
摘要： An apparatus and method are described for synchronizing distribution of packet information. In one embodiment, the invention includes timestamp processing logic to process a transmit time indicator embedded within the packet information, where the transmit time indicator is based on a time reference, and service synchronization queuing logic to hold the packet information until a time offset after the transmit time indicator, where the service synchronization queuing logic is synchronized to the time reference.

8. 发明申请

WO2003067597A3 IMPLEMENTATION OF AN INHIBIT DURING SOFT PROGRAMMING TO TIGHTEN AN ERASE VOLTAGE DISTRIBUTION 审中-公开
公开(公告)号：WO2003067597A3
公开(公告)日：2003-08-14
申请号：PCT/US2003/003710
申请日：2003-02-06
申请人： SANDISK CORPORATION , PAN, Feng , YU,Tat-Kwan, Edgar
发明人： PAN, Feng , YU,Tat-Kwan, Edgar
IPC分类号： G11C16/34
摘要： Methods and apparatus for tightening an erased bit threshold voltage distribution are disclosed. According to one aspect of the present invention, a method for processing erased bits associated with an erased bit distribution which includes an over-erased bit which has a first value that is less than a first threshold voltage value and a bit that has a second value that substantially exceeds a second threshold voltage value includes inhibiting the fast bit. The method also includes applying a soft program pulse to the erased bits such that inhibiting the fast bit substantially prevents the second value from changing and applying the soft program pulse to the over-erased bit substantially causes the first value to increase. In one embodiment, applying the soft program pulse to the over-erased bit substantially causes the first value to increase to a value that is greater than or equal to the first threshold voltage value.

9. 发明申请

WO9939303A9 METHOD AND SYSTEM FOR COMPUTING 8X8 DCT/IDCT AND A VLSI IMPLEMENTATION 审中-公开
标题翻译：用于计算8X8 DCT / IDCT和VLSI实现的方法和系统
公开(公告)号：WO9939303A9
公开(公告)日：1999-10-07
申请号：PCT/US9902186
申请日：1999-02-02
申请人： UNIV PENNSYLVANIA , PAN FENG
发明人： PAN FENG
IPC分类号： G06F17/14 , G06K9/36 , G06K9/46
CPC分类号： G06F17/147
摘要： A method and system for computing 2-D DCT/IDCT which is easy to omplement with VLSI technology to achieve high throughput to meet the requirements of high definition video processing in real time is described. A direct 2-D matrix factorization approach is utilized to compute the 2-D DCT/IDCT. The 8x8 DCT/IDCT is computed through four 4x4 matrix multiplication sub-blocks (1320, 1330, 1340, 1350). Each sub-block is half the size of the original 8x8 size and therefore requires a much lower number of multiplications. Additionally, each sub-block can be implemented independently with localized interconnection so that parallelism can be exploited and a much higher DCT/IDCT throughput can be achieved.
摘要翻译：描述了一种用于计算2D-DCT / IDCT的方法和系统，其易于利用VLSI技术来实现，以实现高吞吐量以实时满足高清晰度视频处理的要求。使用直接的2-D矩阵因式分解方法来计算2-D DCT / IDCT。通过四个4×4矩阵乘法子块（1320,1330,1340,1350）计算8×8 DCT / IDCT。每个子块的大小是原始8x8尺寸的一半，因此需要较少数量的乘法。此外，每个子块可以通过局部互连独立实现，从而可以利用并行性，并且可以实现更高的DCT / IDCT吞吐量。

10. 发明申请

WO2012044424A1 HIGH VOLTAGE SWITCH SUITABLE FOR USE IN FLASH MEMORY 审中-公开
标题翻译：高电压开关适用于闪存存储器
公开(公告)号：WO2012044424A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/049418
申请日：2011-08-26
申请人： SANDISK TECHNOLOGIES INC. , HUYNH, Jonathan Hoang , PAN, Feng
发明人： HUYNH, Jonathan Hoang , PAN, Feng
IPC分类号： G11C8/08 , G11C16/08 , H03K17/06
CPC分类号： G11C16/08 , G11C8/08 , H03K17/063
摘要： A high voltage switch is presented that, rather than relying upon a charge pump to boost the voltage applied to the switches gate in order to compensate for the switch's threshold voltage, a combination of high voltage devices to eliminate the threshold voltage from the switch. This will save on the needed circuit area and reduce the current and, consequently, power consumption. In the exemplary embodiment, the switch circuit passes an input voltage from an input node to an output node in response to an enable signal. The switch includes a level shifter connected to the input node and is connected to receive the enable signal to provide the input voltage as output when the enable signal is asserted. The circuit also includes a first depletion type NMOS transistor that is connected between the input node and a first intermediate node and having a gate connected to receive the output of the level shifter, and a PMOS transistor that is connected between the first intermediate node and the output node and having a gate connected to receive an inverted form of the enable signal.
摘要翻译：提出了一种高压开关，其不是依赖于电荷泵来升高施加到开关栅极的电压，以便补偿开关的阈值电压，高电压装置的组合以消除来自开关的阈值电压。这将节省所需的电路面积，并减少电流，从而降低功耗。在示例性实施例中，响应于使能信号，开关电路将输入电压从输入节点传递到输出节点。开关包括连接到输入节点的电平移位器，并连接以接收使能信号，以在使能信号被断言时提供输入电压作为输出。电路还包括第一耗尽型NMOS晶体管，其连接在输入节点和第一中间节点之间，并且具有连接以接收电平移位器的输出的栅极，以及连接在第一中间节点和第二中间节点之间的PMOS晶体管输出节点并且具有连接的栅极以接收使能信号的反相形式。

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