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1. 发明申请

WO2014046887A1 BLOCK AND PAGE LEVEL BAD BIT LINE AND BITS SCREENING METHOD FOR NON-VOLATILE MEMORY 审中-公开
标题翻译： BLOCK AND PAGE LEVEL BAD BIT LINE AND BITS SCREENING METHOD FOR NON-VOLATILY MEMORY
公开(公告)号：WO2014046887A1
公开(公告)日：2014-03-27
申请号：PCT/US2013/058470
申请日：2013-09-06
申请人： SANDISK TECHNOLOGIES, INC. , WAN, Jun , LEI, Bo , PAN, Feng , SUN, Yongke
发明人： WAN, Jun , LEI, Bo , PAN, Feng , SUN, Yongke
IPC分类号： G11C29/02 , G11C29/44 , G11C7/10 , G11C11/56 , G11C16/10 , G11C16/24 , G11C16/34
CPC分类号： G11C16/349 , G11C7/1006 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/00 , G11C16/10 , G11C16/24 , G11C16/3409 , G11C16/3413 , G11C16/3418 , G11C16/3422 , G11C16/3431 , G11C16/3445 , G11C16/345 , G11C16/3459 , G11C29/025 , G11C29/44 , G11C2029/1204
摘要： A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.
摘要翻译：编程过程评估块的NAND串以检测有缺陷的NAND串，例如具有缺陷存储元件的NAND串。可以存储识别有缺陷的NAND串的状态位。要写入NAND串的原始数据被修改，使得不会发生有缺陷的NAND串的编程。例如，将要编程到较高数据状态的有缺陷的NAND串中的存储元件的一些写入数据修改（例如翻转），使得不需要存储元件的编程。随后，当执行读取操作时，例如通过使用纠错码解码，将翻转的位翻转回其原始值。在擦除处理中，进行有缺陷的NAND串的计数并用于调整验证测试的通过条件。

2. 发明申请

WO2013138199A1 NON-VOLATILE STORAGE WITH READ PROCESS THAT REDUCES DISTURB 审中-公开
标题翻译：具有读取过程的非易失性存储，减少了干扰
公开(公告)号：WO2013138199A1
公开(公告)日：2013-09-19
申请号：PCT/US2013/029991
申请日：2013-03-08
申请人： SANDISK TECHNOLOGIES, INC. , LEI, Bo , WAN, Jun , PAN, Feng
发明人： LEI, Bo , WAN, Jun , PAN, Feng
IPC分类号： G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3427
摘要： A apparatus and process for reading data from non-volatile storage includes applying a read compare signal to a selected data memory cell of a NAND string, applying a first set of one or more read pass voltages to unselected data memory cells at both ends of the NAND string and applying a second set of one or more read pass voltages to unselected data memory cells between both ends of the NAND string and on both sides of the selected data memory cell. The second set of one or more read pass voltages are all higher than the first set of one or more read pass voltages.
摘要翻译：用于从非易失性存储器读取数据的装置和处理包括将读取的比较信号应用于NAND串的所选择的数据存储单元，将第一组一个或多个读取通过电压施加到未读选择数据存储单元的两端 NAND串，并且将第二组一个或多个读取通过电压施加到NAND串的两端和所选数据存储单元的两侧之间的未选择的数据存储单元。第一组一个或多个读通道电压都高于一个或多个读通道电压的第一组。

3. 发明申请

WO2012044424A1 HIGH VOLTAGE SWITCH SUITABLE FOR USE IN FLASH MEMORY 审中-公开
标题翻译：高电压开关适用于闪存存储器
公开(公告)号：WO2012044424A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/049418
申请日：2011-08-26
申请人： SANDISK TECHNOLOGIES INC. , HUYNH, Jonathan Hoang , PAN, Feng
发明人： HUYNH, Jonathan Hoang , PAN, Feng
IPC分类号： G11C8/08 , G11C16/08 , H03K17/06
CPC分类号： G11C16/08 , G11C8/08 , H03K17/063
摘要： A high voltage switch is presented that, rather than relying upon a charge pump to boost the voltage applied to the switches gate in order to compensate for the switch's threshold voltage, a combination of high voltage devices to eliminate the threshold voltage from the switch. This will save on the needed circuit area and reduce the current and, consequently, power consumption. In the exemplary embodiment, the switch circuit passes an input voltage from an input node to an output node in response to an enable signal. The switch includes a level shifter connected to the input node and is connected to receive the enable signal to provide the input voltage as output when the enable signal is asserted. The circuit also includes a first depletion type NMOS transistor that is connected between the input node and a first intermediate node and having a gate connected to receive the output of the level shifter, and a PMOS transistor that is connected between the first intermediate node and the output node and having a gate connected to receive an inverted form of the enable signal.
摘要翻译：提出了一种高压开关，其不是依赖于电荷泵来升高施加到开关栅极的电压，以便补偿开关的阈值电压，高电压装置的组合以消除来自开关的阈值电压。这将节省所需的电路面积，并减少电流，从而降低功耗。在示例性实施例中，响应于使能信号，开关电路将输入电压从输入节点传递到输出节点。开关包括连接到输入节点的电平移位器，并连接以接收使能信号，以在使能信号被断言时提供输入电压作为输出。电路还包括第一耗尽型NMOS晶体管，其连接在输入节点和第一中间节点之间，并且具有连接以接收电平移位器的输出的栅极，以及连接在第一中间节点和第二中间节点之间的PMOS晶体管输出节点并且具有连接的栅极以接收使能信号的反相形式。

4. 发明申请

WO2012044418A1 LEVEL SHIFTER WITH SHOOT-THROUGH CURRENT ISOLATION 审中-公开
标题翻译：水平切换器，具有穿孔电流隔离
公开(公告)号：WO2012044418A1
公开(公告)日：2012-04-05
申请号：PCT/US2011/049109
申请日：2011-08-25
申请人： SANDISK TECHNOLOGIES INC. , HUYNH, Jonathan, Hoang , PAN, Feng , NGUYEN, Qui, Vi , PHAM, Trung
发明人： HUYNH, Jonathan, Hoang , PAN, Feng , NGUYEN, Qui, Vi , PHAM, Trung
IPC分类号： G11C16/08 , G11C16/30 , G11C5/14 , G11C8/08
CPC分类号： G11C16/08 , G11C16/30 , H03K19/0013 , H03K19/018521
摘要： A level shifter circuit suitable for high voltage applications with shoot-through current isolation is presented. The level shifter receives a first enable signal and receives an input voltage at a first node and supplies an output voltage at a second node. The circuit provides the output voltage from the input voltage in response to the first enable signal being asserted and sets the output node to a low voltage value when the first enable signal is de-asserted. The level shifting circuit includes a depletion type NMOS transistor, having a gate connected to the output node, and a PMOS transistor, having a gate connected to the first enable signal. It also includes a first resistive element that is distinct from the NMOS and PMOS transistors. The NMOS transistor, the PMOS transistor and the first resistive elements are connected in series between the first and second nodes, with the NMOS transistor being connected to the first node. The level shifter further includes a discharge circuit connected to the second node and to receive a second enable signal. The second enable signal is asserted when the first enable signal is de-asserted and is asserted when the first enable signal is de-asserted, and the discharge circuit connects the second node to the low voltage value when the second enable signal is asserted and isolates the second node from ground when the second enable signal is de-asserted.
摘要翻译：提出了适用于直流电流隔离的高电压应用的电平移位电路。电平移位器接收第一使能信号并在第一节点处接收输入电压，并在第二节点处提供输出电压。响应于第一使能信号被断言，电路提供来自输入电压的输出电压，并且当第一使能信号被解除置位时，将输出节点设置为低电压值。电平移位电路包括具有连接到输出节点的栅极的耗尽型NMOS晶体管和具有连接到第一使能信号的栅极的PMOS晶体管。它还包括与NMOS和PMOS晶体管不同的第一电阻元件。 NMOS晶体管，PMOS晶体管和第一电阻元件串联连接在第一和第二节点之间，NMOS晶体管连接到第一节点。电平移位器还包括连接到第二节点并且接收第二使能信号的放电电路。当第一使能信号被解除置位时，第二使能信号被置位，并且当第一使能信号被断言时被断言，并且当第二使能信号被断言时，放电电路将第二节点连接到低电压值当第二使能信号被取消断言时，来自接地的第二节点。

5. 发明申请

WO2012154341A1 VARIABLE RESISTANCE SWITCH SUITABLE FOR SUPPLYING HIGH VOLTAGE TO DRIVE LOAD 审中-公开
标题翻译：可变电阻开关适用于提供高电压到驱动负载
公开(公告)号：WO2012154341A1
公开(公告)日：2012-11-15
申请号：PCT/US2012/032398
申请日：2012-04-05
申请人： SANDISK TECHNOLOGIES INC. , HUYNH, Jonathan Hoang , PAN, Feng , HTOO, Khin
发明人： HUYNH, Jonathan Hoang , PAN, Feng , HTOO, Khin
IPC分类号： G11C5/14 , G11C8/08 , G11C16/08 , G11C16/12 , H02M3/07
CPC分类号： G11C8/08 , G11C5/145 , G11C16/08 , G11C16/12
摘要： A circuit for supplying a high voltage to load is described. An example of such a circuit could be used in the peripheral circuitry of a non-volatile memory device for supplying a program voltage from a charge pump to a selected word line. The circuit includes a charge pump that generates the high voltage and decoding circuitry that is connected to receive this high voltage and selectively apply it to a load. The decoding circuitry receives the high voltage through a switch, where the switch is of a variable resistance that progressively passes the high voltage in response to a control signal. In a particular example, the switch includes a transistor connected between the charge pump and the decoding circuitry, where the control gate of the transistor is connected to the output of a second charge pump that is connected to receive the high voltage and a settable clock signal as its inputs.
摘要翻译：描述用于提供高电压负载的电路。这种电路的示例可以用在非易失性存储器件的外围电路中，用于将电荷泵的编程电压提供给选定的字线。电路包括电荷泵，其产生连接以接收该高电压并选择性地将其施加到负载的高电压和解码电路。解码电路通过开关接收高电压，其中开关是响应于控制信号逐渐通过高电压的可变电阻。在特定示例中，开关包括连接在电荷泵和解码电路之间的晶体管，其中晶体管的控制栅极连接到连接以接收高电压的第二电荷泵的输出端和可设置的时钟信号作为其输入。

6. 发明申请

WO2012087532A1 CHARGE PUMP SYSTEMS WITH REDUCTION IN INEFFICIENCIES DUE TO CHARGE SHARING BETWEEN CAPACITANCES 审中-公开
标题翻译：充电泵系统由于电容之间的充电共享而在无功中减少
公开(公告)号：WO2012087532A1
公开(公告)日：2012-06-28
申请号：PCT/US2011/062890
申请日：2011-12-01
申请人： SANDISK TECHNOLOGIES INC. , PAN, Feng , HUYNH, Jonathan, H.
发明人： PAN, Feng , HUYNH, Jonathan, H.
IPC分类号： H02M3/07
CPC分类号： H02M3/07
摘要： Improvements in the efficiency of two charge pump designs are presented. As a charge pump switches between modes, capacitances are charged. Due to charge sharing between capacitances, inefficiencies are introduced. Techniques for reducing these inefficiencies are presented for two different charge pump designs are presented. For a clock voltage doubler type of pump, a four phase clock scheme is introduced to pre-charge the output nodes of the pump's legs. For a pump design where a set of capacitances are connected in series to supply the output during the charging phase, one or more pre-charging phases are introduced after the reset phase, but before the charging phase. In this pre-charge phase, the bottom plate of a capacitor is set to the high voltage level prior to being connected to the top plate of the preceding capacitor in the series.
摘要翻译：介绍了两种电荷泵设计效率的提高。当电荷泵在模式之间切换时，电容被充电。由于电容之间的电荷共享，导致低效率。提出了降低这些低效率的技术，介绍了两种不同的电荷泵设计。对于时钟倍压器类型的泵，引入四相时钟方案以对泵的输出节点预充电。对于其中一组电容串联连接以在充电阶段期间提供输出的泵设计，在复位阶段之后但在充电阶段之前引入一个或多个预充电阶段。在该预充电阶段中，将电容器的底板在连接到串联的前一电容器的顶板之前设置为高电压电平。

7. 发明申请

WO2012006160A1 DETECTION OF WORD-LINE LEAKAGE IN MEMORY ARRAYS: CURRENT BASED APPROACH 审中-公开
标题翻译：检测记忆阵列中的字线泄漏：基于当前的方法
公开(公告)号：WO2012006160A1
公开(公告)日：2012-01-12
申请号：PCT/US2011/042382
申请日：2011-06-29
申请人： SANDISK TECHNOLOGIES INC. , LI, Yan , LEE, Dana , HUYNH, Jonathan H. , PAN, Feng , POPURI, Viswakiran , CAZZANIGA, Marco
发明人： LI, Yan , LEE, Dana , HUYNH, Jonathan H. , PAN, Feng , POPURI, Viswakiran , CAZZANIGA, Marco
IPC分类号： G11C29/02
CPC分类号： G11C29/02 , G11C16/04 , G11C29/025 , G11C29/028 , G11C2029/5006
摘要： Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.
摘要翻译：提供技术和相应的电路用于检测存储器阵列中的字线泄漏。在示例性实施例中，使用电容分压器将高压降转换成可与参考电压进行比较的低电压降，以确定由于泄漏引起的电压降。片上自校准方法可以帮助确保这种检测泄漏极限的技术的准确性。在其他实施例中，将由未被选择的所有字线施加到阵列的高电压的参考阵列绘制的电流与施加高电压的阵列和一个或多个选定的字线所绘制的电流进行比较。在这些基于当前的实施例中，参考阵列可以是不同的阵列，或与用于测试所选择的阵列相同的阵列。

8. 发明申请

WO2009151798A1 CHARGE PUMP WITH Vt CANCELLATION THROUGH PARALLEL STRUCTURE 审中-公开
标题翻译：充电泵通过并联结构取消
公开(公告)号：WO2009151798A1
公开(公告)日：2009-12-17
申请号：PCT/US2009/041714
申请日：2009-04-24
申请人： SANDISK CORPORATION , PAN, Feng , HUYNH, Jonathan, H.
发明人： PAN, Feng , HUYNH, Jonathan, H.
IPC分类号： H02M3/07
CPC分类号： H02M3/07
摘要： A charge pump circuit for generating an output voltage is described. The charge pump includes an output generation section and a threshold voltage cancellation section, where these sections have the same structure including a first branch, which receives a first clock signal and provides a first output, and a second branch, which receives a second clock signal and provides a second output. The charge pump circuit also includes first and second transistors, where the first and second outputs of the output generation stage are respectively connected through the first and second transistors to provide the output voltage of the charge pump, and where the first and second outputs of the threshold voltage cancellation stage are respectively connected to the control gate the first and second transistors.
摘要翻译：描述用于产生输出电压的电荷泵电路。电荷泵包括输出产生部分和阈值电压消除部分，其中这些部分具有相同的结构，包括接收第一时钟信号并提供第一输出的第一分支和接收第二时钟信号的第二分支并提供第二输出。电荷泵电路还包括第一和第二晶体管，其中输出发生级的第一和第二输出分别通过第一和第二晶体管连接以提供电荷泵的输出电压，并且其中第一和第二输出的第一和第二输出阈值电压消除级分别与第一和第二晶体管的控制栅极连接。

9. 发明申请

WO2004023821A1 A METHOD AND AN APPARATUS FOR CONTROLLING THE RATE OF A VIDEO SEQUENCE; A VIDEO ENCODING DEVICE 审中-公开
标题翻译：一种用于控制视频序列速率的方法和装置; 视频编码器
公开(公告)号：WO2004023821A1
公开(公告)日：2004-03-18
申请号：PCT/SG2002/000206
申请日：2002-09-05
申请人： LABORATORIES FOR INFORMATION TECHNOLOGY , LI, Zhengguo , PAN, Feng , LIM, Keng, Pang , WU, Dajun , YU, Rongshan , FENG, Genan , WANG, Dusheng
发明人： LI, Zhengguo , PAN, Feng , LIM, Keng, Pang , WU, Dajun , YU, Rongshan , FENG, Genan , WANG, Dusheng
IPC分类号： H04N7/50
CPC分类号： H04N19/587 , H04N19/115 , H04N19/124 , H04N19/132 , H04N19/147 , H04N19/149 , H04N19/152 , H04N19/156 , H04N19/159 , H04N19/164 , H04N19/172 , H04N19/61
摘要： A method for rate control for encoding video sequence, wherein the video sequence comprises a plurality of Group Of Pictures, wherein each Group of Picture comprises at least and I-frame and an Inter-frame, the rate control method comprising the following steps for the encoding of the. Inter-frame in the Group of Picture: determining a desired frame rate based on an available bandwidth of a channel for transmitting the video sequence and an available computational resources for the encoding process; determining a target buffer level based on the desired frame rate and the position of the Inter-frame with respect to the I-frame; and determining a target bit rate based on the target buffer level and the available channel bandwidth, wherein the target bit rate is used for controlling the rate of encoding the video sequence.
摘要翻译：一种用于编码视频序列的速率控制的方法，其中所述视频序列包括多个图像组，其中每组图片至少包括I帧和帧间帧，所述速率控制方法包括以下步骤：编码的。图像组中的帧间：基于用于发送视频序列的信道的可用带宽和用于编码处理的可用计算资源来确定期望的帧速率; 基于期望的帧速率和帧间相对于I帧的位置来确定目标缓冲器级; 以及基于所述目标缓冲器电平和所述可用信道带宽来确定目标比特率，其中，所述目标比特率用于控制所述视频序列的编码速率。

10. 发明申请

WO2004012458A2 EFFICIENT VIDEO TRANSMISSION 审中-公开
标题翻译：有效的视频传输
公开(公告)号：WO2004012458A2
公开(公告)日：2004-02-05
申请号：PCT/SG2002/000168
申请日：2002-07-26
申请人： NANYANG TECHNOLOGICAL UNIVERSITY , YANG, Xiao, Kang , YU, Rong, Shan , ZHU, Ce , LIM, Keng, Pang , LI, Zheng, Guo , PAN, Feng , FENG, Ge, Nan , WU, Da, Jun , WU, Si
发明人： YANG, Xiao, Kang , YU, Rong, Shan , ZHU, Ce , LIM, Keng, Pang , LI, Zheng, Guo , PAN, Feng , FENG, Ge, Nan , WU, Da, Jun , WU, Si
IPC分类号： H04N7/26
CPC分类号： H04N19/51 , H04N19/557
摘要： A method and system for reducing the complexity of block motion estimation is described. According to the invention, the block distortion measure is determined by calculating a partial error result using a proportion of pixels in the block, comparing the partial error result with a threshold value and rejecting blocks where the partial error result is greater than the threshold value, and calculating a full error result for non-rejected blocks only. The threshold value is a function of the current minimum partial error result, and is preferably the current minimum partial error result multiplied by a threshold constant λ. Another aspect of the invention provides a video transport scheme which exploits the different importance of both GOP and re-synchronisation levels. According to this aspect, an unequal loss protection (ULP) philosophy is utilized. That is, the bit stream data is partitioned into several parts according to different importance, and the parts are unequally protected against packet loss using forward error correction codes.
摘要翻译：描述了一种降低块运动估计复杂度的方法和系统。根据本发明，通过使用块中的像素的比例来计算部分误差结果来确定块失真度量，将部分错误结果与阈值进行比较，并且拒绝部分错误结果大于阈值的块，并仅计算未拒绝块的完整错误结果。阈值是当前最小部分误差结果的函数，并且优选地是当前最小部分误差结果乘以阈值常数λ1。本发明的另一方面提供一种视频传输方案，其利用GOP和重新同步级别的不同重要性。根据这一方面，利用了不平等的损失保护（ULP）理念。也就是说，根据不同的重要性将比特流数据划分成若干部分，并且使用前向纠错码对这些部分进行不均匀的保护以防止丢包。

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