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1. 发明申请

US20100184296A1 Semiconductor device manufacturing method, wafer treatment system, and recording medium 有权
标题翻译：半导体器件制造方法，晶片处理系统和记录介质
公开(公告)号：US20100184296A1
公开(公告)日：2010-07-22
申请号：US12654987
申请日：2010-01-12
申请人： Hidetaka Nambu , Nobuo Hironaga , Futoshi Ota , Toru Yokoyama , Osamu Sugawara , Ryo Satou , Masato Tamura
发明人： Hidetaka Nambu , Nobuo Hironaga , Futoshi Ota , Toru Yokoyama , Osamu Sugawara , Ryo Satou , Masato Tamura
IPC分类号： H01L21/306 , H01L21/3065
CPC分类号： H01L21/67389
摘要： A semiconductor device manufacturing method includes loading plural dry-etched wafers one by one in a container having a side door so as to be disposed substantially horizontally and in layers vertically therein; and blowing out a purge gas horizontally to those wafers loaded in the container for 30 sec or more after all the subject wafers are loaded in the container while the side door is open.
摘要翻译：半导体器件制造方法包括：将多个干蚀刻晶片一个接一个地装载在具有侧门的容器中，以便基本上水平布置并且在其中垂直地设置; 并且在侧门打开时将所有的被摄体晶片装载到容器中之后，将装载在容器中的那些晶片水平地吹扫吹扫气体30秒以上。

2. 发明授权

US07581149B2 Scan chain extracting method, test apparatus, circuit device, and scan chain extracting program 有权
标题翻译：扫描链提取方法，测试仪器，电路设备和扫描链提取程序
公开(公告)号：US07581149B2
公开(公告)日：2009-08-25
申请号：US11410155
申请日：2006-04-25
申请人： Osamu Sugawara
发明人： Osamu Sugawara
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A scan-chain extracting method of the present invention includes a defining step of defining control-circuit scan chains provided in a test control circuit; an initial-value setting step of setting an initial value for the sequence circuit devices of the control-circuit scan chains; a state setting step of setting the scan chains to through states; an extracting step of extracting data regarding the scan chains; a determining step of determining whether or not data regarding all the scan chains have been extracted; and a changing step of changing the initial value for the sequence circuit devices included in the test control circuit connected to the sequence circuit devices located at the start points of the scan chains, when it is determined that not all data regarding the scan chains have been extracted.
摘要翻译：本发明的扫描链提取方法包括定义在测试控制电路中提供的控制电路扫描链的步骤; 初始值设定步骤，设定控制电路扫描链的顺序电路器件的初始值; 将扫描链设置为通过状态的状态设置步骤; 提取与扫描链相关的数据的提取步骤; 确定是否已经提取关于所有扫描链的数据的确定步骤; 以及改变步骤，当确定不是所有关于扫描链的所有数据都已经被扫描时，改变包括在连接到位于扫描链的起始点处的序列电路装置的测试控制电路中的序列电路装置的初始值提取。

3. 发明授权

US08349087B2 Semiconductor device manufacturing method, wafer treatment system, and recording medium 有权
标题翻译：半导体器件制造方法，晶片处理系统和记录介质
公开(公告)号：US08349087B2
公开(公告)日：2013-01-08
申请号：US12654987
申请日：2010-01-12
申请人： Hidetaka Nambu , Nobuo Hironaga , Futoshi Ota , Toru Yokoyama , Osamu Sugawara , Ryo Satou , Masato Tamura
发明人： Hidetaka Nambu , Nobuo Hironaga , Futoshi Ota , Toru Yokoyama , Osamu Sugawara , Ryo Satou , Masato Tamura
IPC分类号： B08B3/12 , B08B6/00 , B08B7/00 , B08B7/02 , C25F1/00 , C25F3/30 , C25F5/00
CPC分类号： H01L21/67389
摘要： A semiconductor device manufacturing method includes loading plural dry-etched wafers one by one in a container having a side door so as to be disposed substantially horizontally and in layers vertically therein; and blowing out a purge gas horizontally to those wafers loaded in the container for 30 sec or more after all the subject wafers are loaded in the container while the side door is open.
摘要翻译：半导体器件制造方法包括：将多个干蚀刻晶片一个接一个地装载在具有侧门的容器中，以便基本上水平布置并且在其中垂直地设置; 并且在侧门打开时将所有的被摄体晶片装载到容器中之后，将装载在容器中的那些晶片水平地吹扫吹扫气体30秒以上。

4. 发明授权

US08264469B2 Touch panel and display unit 有权
标题翻译：触摸面板和显示单元
公开(公告)号：US08264469B2
公开(公告)日：2012-09-11
申请号：US12506665
申请日：2009-07-21
申请人： Kiyohiro Kimura , Kazuhiro Miura , Harutoshi Oikawa , Osamu Sugawara , Toshinori Kadowaki
发明人： Kiyohiro Kimura , Kazuhiro Miura , Harutoshi Oikawa , Osamu Sugawara , Toshinori Kadowaki
IPC分类号： G06F3/041
CPC分类号： G06F3/044 , G06F3/045 , H05K3/361 , H05K2203/1572
摘要： A touch panel capable of decreasing concavity and convexity generated on the surface and a display unit including the same are provided. The touch panel includes: a first spacer layer on both side faces of a first wiring layer provided on a first transparent substrate; and a second wiring layer on both side faces of a second wiring layer provided on a second transparent substrate. The touch panel also includes a flexible printed circuit board in a gap between the first transparent substrate and the second transparent substrate and in a region including at least part of a region not provided with the adhesion layer in the region opposed to the first wiring layer, the second wiring layer, the first spacer layer, and the second spacer layer.
摘要翻译：提供能够减小表面上产生的凹凸的触摸面板和包括该触摸面板的显示单元。触摸面板包括：设置在第一透明基板上的第一布线层的两个侧面上的第一间隔层; 以及设置在第二透明基板上的第二布线层的两个侧面上的第二布线层。触摸面板还包括在第一透明基板和第二透明基板之间的间隙中的柔性印刷电路板，并且在与第一布线层相对的区域中包括至少部分未设置有粘合层的区域的区域中，第二布线层，第一间隔层和第二间隔层。

5. 发明申请

US20100026648A1 TOUCH PANEL AND DISPLAY UNIT 有权
标题翻译：触摸板和显示单元
公开(公告)号：US20100026648A1
公开(公告)日：2010-02-04
申请号：US12506665
申请日：2009-07-21
申请人： Kiyohiro Kimura , Kazuhiro Miura , Harutoshi Oikawa , Osamu Sugawara , Toshinori Kadowaki
发明人： Kiyohiro Kimura , Kazuhiro Miura , Harutoshi Oikawa , Osamu Sugawara , Toshinori Kadowaki
IPC分类号： G06F3/041
CPC分类号： G06F3/044 , G06F3/045 , H05K3/361 , H05K2203/1572
摘要： A touch panel capable of decreasing concavity and convexity generated on the surface and a display unit including the same are provided. The touch panel includes: a first spacer layer on both side faces of a first wiring layer provided on a first transparent substrate; and a second wiring layer on both side faces of a second wiring layer provided on a second transparent substrate. The touch panel also includes a flexible printed circuit board in a gap between the first transparent substrate and the second transparent substrate and in a region including at least part of a region not provided with the adhesion layer in the region opposed to the first wiring layer, the second wiring layer, the first spacer layer, and the second spacer layer.
摘要翻译：提供能够减小表面上产生的凹凸的触摸面板和包括该触摸面板的显示单元。触摸面板包括：设置在第一透明基板上的第一布线层的两个侧面上的第一间隔层; 以及设置在第二透明基板上的第二布线层的两个侧面上的第二布线层。触摸面板还包括在第一透明基板和第二透明基板之间的间隙中的柔性印刷电路板，并且在与第一布线层相对的区域中包括至少部分未设置有粘合层的区域的区域中，第二布线层，第一间隔层和第二间隔层。

6. 发明申请

US20070174747A1 Scan chain extracting method, test apparatus, circuit device, and scan chain extracting program 有权
标题翻译：扫描链提取方法，测试仪器，电路设备和扫描链提取程序
公开(公告)号：US20070174747A1
公开(公告)日：2007-07-26
申请号：US11410155
申请日：2006-04-25
申请人： Osamu Sugawara
发明人： Osamu Sugawara
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A scan-chain extracting method of the present invention includes a defining step of defining control-circuit scan chains provided in a test control circuit; an initial-value setting step of setting an initial value for the sequence circuit devices of the control-circuit scan chains; a state setting step of setting the scan chains to through states; an extracting step of extracting data regarding the scan chains; a determining step of determining whether or not data regarding all the scan chains have been extracted; and a changing step of changing the initial value for the sequence circuit devices included in the test control circuit connected to the sequence circuit devices located at the start points of the scan chains, when it is determined that not all data regarding the scan chains have been extracted.
摘要翻译：本发明的扫描链提取方法包括定义在测试控制电路中提供的控制电路扫描链的步骤; 初始值设定步骤，设定控制电路扫描链的顺序电路器件的初始值; 将扫描链设置为通过状态的状态设置步骤; 提取与扫描链相关的数据的提取步骤; 确定是否已经提取关于所有扫描链的数据的确定步骤; 以及改变步骤，当确定不是所有关于扫描链的所有数据都已经被扫描时，改变包括在连接到位于扫描链的起始点处的序列电路装置的测试控制电路中的序列电路装置的初始值提取。

7. 发明授权

US06599811B1 Semiconductor device having a shallow isolation trench 有权
标题翻译：具有浅隔离沟槽的半导体器件
公开(公告)号：US06599811B1
公开(公告)日：2003-07-29
申请号：US09249556
申请日：1999-02-12
申请人： Kenya Kazama , Osamu Sugawara
发明人： Kenya Kazama , Osamu Sugawara
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76229
摘要： A method for forming a semiconductor device having an isolation trench for separation of element regions includes the steps of forming a pad oxide film and a silicon nitride film on a silicon substrate, forming an isolation trench by using the silicon nitride film as a mask, forming consecutively a thermal oxide film, CVD oxide film and a bias oxide film in the isolation trench, removing the films above a specified level of the silicon substrate to leave the isolation trench filled with oxide films. The bias oxide film is formed by a high-density plasma CVD technique. The silicon surface is protected by the CVD oxide film against the plasma damage during the high-density CVD step, thereby obtaining excellent characteristics of transistors.
摘要翻译：用于形成具有用于分离元件区域的隔离沟槽的半导体器件的方法包括以下步骤：在硅衬底上形成衬垫氧化膜和氮化硅膜，通过使用氮化硅膜作为掩模形成隔离沟槽，形成在隔离沟槽中连续地形成热氧化膜，CVD氧化物膜和偏置氧化膜，将膜移至高于硅衬底的指定电平以留下填充有氧化物膜的隔离沟槽。偏置氧化膜通过高密度等离子体CVD技术形成。在高密度CVD步骤期间，硅表面受到CVD氧化膜的抵抗等离子体损伤的保护，从而获得晶体管的优异特性。

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