专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080224196A1 SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS FOR THE SAME 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：US20080224196A1
公开(公告)日：2008-09-18
申请号：US12040315
申请日：2008-02-29
申请人： Tomohiko HIGASHINO , Nobuyuki KATSUKI , Yasuhiro KAWAKATSU , Michihiro KOBAYASHI
发明人： Tomohiko HIGASHINO , Nobuyuki KATSUKI , Yasuhiro KAWAKATSU , Michihiro KOBAYASHI
IPC分类号： H01L27/11 , H01L21/70
CPC分类号： G11C11/4125
摘要： A semiconductor device includes a first inverter, a second inverter, and an inner wiring connecting the inverters, in which the inner wiring forms a capacitor element, and the capacitor element includes an interlayer insulation film having an aperture on a semiconductor substrate, a lower electrode covering a bottom wall and a side wall of the aperture, the bottom wall being the semiconductor substrate and the side wall being a part of the interlayer insulation film, a capacitor insulation film arranged on the lower electrode and a part of the interlayer insulation film, the capacitor insulation film covering corners of the capacitor insulation film, the corners being situated at opposite side of the semiconductor substrate, and an upper electrode on the capacitor insulation film, the upper electrode covering the aperture.
摘要翻译：半导体器件包括第一反相器，第二反相器和连接反相器的内部布线，其中内部布线形成电容器元件，并且电容器元件包括在半导体衬底上具有孔的层间绝缘膜，下部电极覆盖孔的底壁和侧壁，底壁是半导体衬底，侧壁是层间绝缘膜的一部分，布置在下电极上的电容器绝缘膜和层间绝缘膜的一部分，电容器绝缘膜覆盖电容器绝缘膜的拐角，拐角位于半导体衬底的相对侧，电容器绝缘膜上的上电极，覆盖孔的上电极。

2. 发明申请

US20070243684A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFATURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070243684A1
公开(公告)日：2007-10-18
申请号：US11767074
申请日：2007-06-22
申请人： Nobuyuki KATSUKI , Atsushi OGA , Shuuichi SENOU , Noriyuki OTA , Masahiro YOSHIDA , Kenta ARAI , Atsushi NAKAGAWA , Tomotaka MURAKAMI
发明人： Nobuyuki KATSUKI , Atsushi OGA , Shuuichi SENOU , Noriyuki OTA , Masahiro YOSHIDA , Kenta ARAI , Atsushi NAKAGAWA , Tomotaka MURAKAMI
IPC分类号： H01L21/8234
CPC分类号： H01L27/088 , H01L21/823412 , H01L29/1045
摘要： The semiconductor device includes a reference voltage generator circuit and a circuit different from the reference voltage generator circuit. A semiconductor element of the reference voltage generator circuit has a channel region where a substrate impurity concentration is substantially uniform at least in the vicinity of a drain region. A semiconductor element of the circuit different from the reference voltage generator circuit has a channel region where a substrate impurity concentration is higher than in other part of the region at least in the drain region.
摘要翻译：半导体器件包括参考电压发生器电路和与参考电压发生器电路不同的电路。参考电压发生器电路的半导体元件具有至少在漏极区附近衬底杂质浓度基本均匀的沟道区。与参考电压发生器电路不同的电路的半导体元件具有至少在漏极区域中衬底杂质浓度高于该区域的其它部分的沟道区域。

3. 发明申请

US20050087774A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050087774A1
公开(公告)日：2005-04-28
申请号：US10969349
申请日：2004-10-21
申请人： Nobuyuki Katsuki , Atsushi Oga , Shuuichi Senou , Noriyuki Ota , Masahiro Yoshida , Kenta Arai , Atsushi Nakagawa , Tomotaka Murakami
发明人： Nobuyuki Katsuki , Atsushi Oga , Shuuichi Senou , Noriyuki Ota , Masahiro Yoshida , Kenta Arai , Atsushi Nakagawa , Tomotaka Murakami
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/088 , H01L27/148 , H01L29/10 , H01L29/78
CPC分类号： H01L27/088 , H01L21/823412 , H01L29/1045
摘要： The semiconductor device includes a reference voltage generator circuit and a circuit different from the reference voltage generator circuit. A semiconductor element of the reference voltage generator circuit has a channel region where a substrate impurity concentration is substantially uniform at least in the vicinity of a drain region. A semiconductor element of the circuit different from the reference voltage generator circuit has a channel region where a substrate impurity concentration is higher than in other part of the region at least in the drain region.
摘要翻译：半导体器件包括参考电压发生器电路和与参考电压发生器电路不同的电路。参考电压发生器电路的半导体元件具有至少在漏极区附近衬底杂质浓度基本均匀的沟道区。与参考电压发生器电路不同的电路的半导体元件具有至少在漏极区域中衬底杂质浓度高于该区域的其它部分的沟道区域。

4. 发明授权

US07719042B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07719042B2
公开(公告)日：2010-05-18
申请号：US11812192
申请日：2007-06-15
申请人： Yasuhiro Kawakatsu , Hitoshi Abiko , Hirofumi Nikaido , Nobuyuki Katsuki , Michihiro Kobayashi
发明人： Yasuhiro Kawakatsu , Hitoshi Abiko , Hirofumi Nikaido , Nobuyuki Katsuki , Michihiro Kobayashi
IPC分类号： H01L27/108
CPC分类号： H01L27/1104 , H01L27/11
摘要： A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.
摘要翻译：下电极从上电极和电容器膜的公共端面向外突出。由与电容器膜不同的材料制成的保护膜沉积在端面外部的一部分下部电极的顶部。保护膜也从端面向内延伸到一定距离的位置，使其保持在电容器膜和下电极之间。由于存在保护膜，因此电容器膜具有靠近端面的台阶表面，这抑制了上电极和电容器膜的蚀刻期间的损坏进展。此外，保护膜防止在下电极中发生损坏。

5. 发明申请

US20080001197A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20080001197A1
公开(公告)日：2008-01-03
申请号：US11812192
申请日：2007-06-15
申请人： Yasuhiro Kawakatsu , Hitoshi Abiko , Hirofumi Nikaido , Nobuyuki Katsuki , Michihiro Kobayashi
发明人： Yasuhiro Kawakatsu , Hitoshi Abiko , Hirofumi Nikaido , Nobuyuki Katsuki , Michihiro Kobayashi
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/1104 , H01L27/11
摘要： A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.
摘要翻译：下电极从上电极和电容器膜的公共端面向外突出。由与电容器膜不同的材料制成的保护膜沉积在端面外部的一部分下部电极的顶部。保护膜也从端面向内延伸到一定距离的位置，使其保持在电容器膜和下电极之间。由于存在保护膜，因此电容器膜具有靠近端面的台阶表面，这抑制了上电极和电容器膜的蚀刻期间的损坏进展。此外，保护膜防止在下电极中发生损坏。

6. 发明授权

US4742115A Heat resistant, thermoplastic resin composition 失效
标题翻译：耐热，热塑性树脂组合物
公开(公告)号：US4742115A
公开(公告)日：1988-05-03
申请号：US762828
申请日：1985-08-06
申请人： Masaaki Mawatari , Syuji Tsuchikawa , Shinichi Kimura , Nobuyuki Katsuki , Mitsuo Abe
发明人： Masaaki Mawatari , Syuji Tsuchikawa , Shinichi Kimura , Nobuyuki Katsuki , Mitsuo Abe
IPC分类号： C08L25/12 , C08L51/04 , C08L63/00 , C08L67/00 , C08L69/00 , C08L71/00 , C08L71/12 , C08L77/00 , C08L81/00 , C08L81/02 , C08L81/06 , C08L71/04
CPC分类号： C08L25/12 , C08L51/04 , C08L71/123 , C08L2205/02 , C08L63/00 , C08L67/00 , C08L69/00 , C08L71/00 , C08L71/12 , C08L77/00 , C08L81/00 , C08L81/02 , C08L81/06 , Y10S525/905
摘要： A heat resistant thermoplastic resin composition comprising (a) 5 to 99% by weight of a poly(phenylene ether), (b) 95 to 1% by weight of a thermoplastic resin which is obtained by polymerizing in the absence of a rubber-like polymer a resin constituent mixture comprising an aromatic alkenyl compound, an alkenyl cyanide compound, and, if necessary, other alkenyl monomers copolymerizable with said monomers, and (c) up to 94% by weight of other styrenic resins, said thermoplastic resin (b) comprising (A) 1-50% by weight of a polymer having an alkenyl cyanide compound content of 1% by weight or more but less than 10% by weight, (B) 1-70% by weight of a polymer having an alkenyl cyanide compound content of 10% by weight or more but less than 20% by weight, (C) 5-90% by weight of a polymer having an alkenyl cyanide compound content of 20% by weight or more but less than 40% by weight, and (D) up to 70% by weight of a polymer having an alkenyl cyanide compound content of 40% by weight or more, and having a total alkenyl cyanide compound content of 10 to 40% by weight and an intrinsic viscosity of preferably 0.1- 1.5 dl/g as measured in methyl ethyl ketone at 30.degree. C. The above thermoplastic resin composition is excellent in not only heat resistance but also impact resistance, thermal stability, painting, and surface gloss of molded article.
摘要翻译：一种耐热性热塑性树脂组合物，其包含（a）5至99重量％的聚（苯醚），（b）95至1重量％的热塑性树脂，其通过在不存在橡胶状的情况下聚合而获得聚合物包含芳族烯基化合物，链烯基氰化物化合物和必要时可与所述单体共聚的其它链烯基单体的树脂组合物混合物，和（c）最多94重量％的其它苯乙烯类树脂，所述热塑性树脂（b）包含（A）1-50重量％的链烯基氰化合物含量为1重量％以上但小于10重量％的聚合物，（B）1-70重量％的具有链烯基氰的聚合物化合物含量为10重量％以上但小于20重量％，（C）5-氰基氰化合物含量为20重量％以上但小于40重量％的聚合物的5-90重量％和（D）至多70重量％的链烯基氰化合物含量为40重量％以上的聚合物，并且在30℃下，在甲基乙基酮中测定的全部链烯基氰化合物含量为10〜40重量％，特性粘度优选为0.1〜1.5dl / g。上述热塑性树脂组合物不仅具有优异的热耐冲击性，也具有耐冲击性，热稳定性，喷涂性和表面光泽度。

7. 发明授权

US08492815B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US08492815B2
公开(公告)日：2013-07-23
申请号：US12652299
申请日：2010-01-05
申请人： Nobuyuki Katsuki
发明人： Nobuyuki Katsuki
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/0207 , H01L27/10855 , H01L27/10888
摘要： A semiconductor memory includes a DRAM having, as seen in planar view, a first bit line and a second bit line formed on a first active area, a first cell contact formed on the first active area, and a first capacitor contact formed on the first cell contact and which is connected to a capacitor. As seen in planar view, the first cell contact is positioned closer to the second bit line than to the first bit line, and the first capacitor contact is formed offset in a direction approaching the first bit line with respect to the first cell contact.
摘要翻译：半导体存储器包括DRAM，如平面图所示，形成在第一有源区上的第一位线和第二位线，形成在第一有源区上的第一单元触点和形成在第一有源区上的第一电容器触点电池接触并连接到电容器。如平面图所示，第一单元触点位于比第一位线更靠近第二位线的位置，并且第一电容器触点形成为相对于第一单元触点接近第一位线的方向偏移。

8. 发明申请

US20100171160A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20100171160A1
公开(公告)日：2010-07-08
申请号：US12652299
申请日：2010-01-05
申请人： Nobuyuki KATSUKI
发明人： Nobuyuki KATSUKI
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/10855 , H01L27/10888
摘要： A semiconductor memory includes a DRAM having, as seen in planar view, a first bit line and a second bit line formed on a first active area, a first cell contact formed on the first active area, and a first capacitor contact formed on the first cell contact and which is connected to a capacitor. As seen in planar view, the first cell contact is positioned closer to the second bit line than to the first bit line, and the first capacitor contact is formed offset in a direction approaching the first bit line with respect to the first cell contact.
摘要翻译：半导体存储器包括DRAM，如平面图所示，形成在第一有源区上的第一位线和第二位线，形成在第一有源区上的第一单元触点和形成在第一有源区上的第一电容器触点电池接触并连接到电容器。如平面图所示，第一单元触点位于比第一位线更靠近第二位线的位置，并且第一电容器触点形成为相对于第一单元触点接近第一位线的方向偏移。

9. 发明申请

US20070278694A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070278694A1
公开(公告)日：2007-12-06
申请号：US11806231
申请日：2007-05-30
申请人： Michihiro Kobayashi , Hirofumi Nikaido , Nobuyuki Katsuki , Yasuhiro Kawakatsu
发明人： Michihiro Kobayashi , Hirofumi Nikaido , Nobuyuki Katsuki , Yasuhiro Kawakatsu
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L21/76816 , H01L21/76895 , H01L23/5226 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： Two interconnect layers are electrically connected while reducing the number of manufacturing steps. A contact plug 9c which is formed into a beaded shape in a layer underlying two interconnects 11C and 11D and which also electrically connects the two interconnects 11C and 11D is included. The two interconnects 11C and 11D are separated to each other and are formed in a same layer. The contact plug 9c is simultaneously formed with a contact plug 9b to be connected to an interconnect 4b and a contact plug 9a to be connected to a source/drain region 6.
摘要翻译：两个互连层电连接，同时减少制造步骤的数量。包括在两个互连11C和11D下面的层中形成为串珠形状并且还电连接两个互连11C和11D的接触插塞9c。两个互连11C和11D彼此分离并且形成在相同的层中。接触插头9c同时形成有接触插头9b，以连接到互连件4b和连接到源极/漏极区域6的接触插塞9a。

10. 发明授权

US06583027B2 Manufacturing method of semiconductor device and designing method of semiconductor device 失效
公开(公告)号：US06583027B2
公开(公告)日：2003-06-24
申请号：US10024157
申请日：2001-12-18
申请人： Noriyuki Ota , Nobuyuki Katsuki
发明人： Noriyuki Ota , Nobuyuki Katsuki
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： When a top surface area for a plurality of dummy patterns 13 and a width for a plurality of trenches 12 are set on the basis of a ratio (an occupation density of the film for polishing in an adjacent region 10) of a total top surface area for raised sections of the film for polishing to a horizontally projected area of the adjacent region 10, it is possible to suppress dishing and erosion and thereby attain a high planarity when a film for polishing is formed on a semiconductor substrate, wherein dummy patterns 13 partitioned by a plurality of trenches 12 are disposed in an element isolation region 11, and planarization by the CMP is applied thereto.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式