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1. 发明申请

US20080224196A1 SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS FOR THE SAME 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：US20080224196A1
公开(公告)日：2008-09-18
申请号：US12040315
申请日：2008-02-29
申请人： Tomohiko HIGASHINO , Nobuyuki KATSUKI , Yasuhiro KAWAKATSU , Michihiro KOBAYASHI
发明人： Tomohiko HIGASHINO , Nobuyuki KATSUKI , Yasuhiro KAWAKATSU , Michihiro KOBAYASHI
IPC分类号： H01L27/11 , H01L21/70
CPC分类号： G11C11/4125
摘要： A semiconductor device includes a first inverter, a second inverter, and an inner wiring connecting the inverters, in which the inner wiring forms a capacitor element, and the capacitor element includes an interlayer insulation film having an aperture on a semiconductor substrate, a lower electrode covering a bottom wall and a side wall of the aperture, the bottom wall being the semiconductor substrate and the side wall being a part of the interlayer insulation film, a capacitor insulation film arranged on the lower electrode and a part of the interlayer insulation film, the capacitor insulation film covering corners of the capacitor insulation film, the corners being situated at opposite side of the semiconductor substrate, and an upper electrode on the capacitor insulation film, the upper electrode covering the aperture.
摘要翻译：半导体器件包括第一反相器，第二反相器和连接反相器的内部布线，其中内部布线形成电容器元件，并且电容器元件包括在半导体衬底上具有孔的层间绝缘膜，下部电极覆盖孔的底壁和侧壁，底壁是半导体衬底，侧壁是层间绝缘膜的一部分，布置在下电极上的电容器绝缘膜和层间绝缘膜的一部分，电容器绝缘膜覆盖电容器绝缘膜的拐角，拐角位于半导体衬底的相对侧，电容器绝缘膜上的上电极，覆盖孔的上电极。

2. 发明申请

US20100171160A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20100171160A1
公开(公告)日：2010-07-08
申请号：US12652299
申请日：2010-01-05
申请人： Nobuyuki KATSUKI
发明人： Nobuyuki KATSUKI
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/10855 , H01L27/10888
摘要： A semiconductor memory includes a DRAM having, as seen in planar view, a first bit line and a second bit line formed on a first active area, a first cell contact formed on the first active area, and a first capacitor contact formed on the first cell contact and which is connected to a capacitor. As seen in planar view, the first cell contact is positioned closer to the second bit line than to the first bit line, and the first capacitor contact is formed offset in a direction approaching the first bit line with respect to the first cell contact.
摘要翻译：半导体存储器包括DRAM，如平面图所示，形成在第一有源区上的第一位线和第二位线，形成在第一有源区上的第一单元触点和形成在第一有源区上的第一电容器触点电池接触并连接到电容器。如平面图所示，第一单元触点位于比第一位线更靠近第二位线的位置，并且第一电容器触点形成为相对于第一单元触点接近第一位线的方向偏移。

3. 发明申请

US20070243684A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFATURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070243684A1
公开(公告)日：2007-10-18
申请号：US11767074
申请日：2007-06-22
申请人： Nobuyuki KATSUKI , Atsushi OGA , Shuuichi SENOU , Noriyuki OTA , Masahiro YOSHIDA , Kenta ARAI , Atsushi NAKAGAWA , Tomotaka MURAKAMI
发明人： Nobuyuki KATSUKI , Atsushi OGA , Shuuichi SENOU , Noriyuki OTA , Masahiro YOSHIDA , Kenta ARAI , Atsushi NAKAGAWA , Tomotaka MURAKAMI
IPC分类号： H01L21/8234
CPC分类号： H01L27/088 , H01L21/823412 , H01L29/1045
摘要： The semiconductor device includes a reference voltage generator circuit and a circuit different from the reference voltage generator circuit. A semiconductor element of the reference voltage generator circuit has a channel region where a substrate impurity concentration is substantially uniform at least in the vicinity of a drain region. A semiconductor element of the circuit different from the reference voltage generator circuit has a channel region where a substrate impurity concentration is higher than in other part of the region at least in the drain region.
摘要翻译：半导体器件包括参考电压发生器电路和与参考电压发生器电路不同的电路。参考电压发生器电路的半导体元件具有至少在漏极区附近衬底杂质浓度基本均匀的沟道区。与参考电压发生器电路不同的电路的半导体元件具有至少在漏极区域中衬底杂质浓度高于该区域的其它部分的沟道区域。

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