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1. 发明授权

US09492856B2 Element wire, electric wire and process for producing element wire 有权
标题翻译：元素线，电线和生产元素线的工艺
公开(公告)号：US09492856B2
公开(公告)日：2016-11-15
申请号：US12073157
申请日：2008-02-29
申请人： Kenichi Hanazaki , Satoru Yoshinaga , Nobuhiro Tsuji
发明人： Kenichi Hanazaki , Satoru Yoshinaga , Nobuhiro Tsuji
IPC分类号： B32B15/02 , B05B5/12 , B21C23/26 , B21C1/00 , B21C37/04
CPC分类号： B21C23/26 , B21C1/00 , B21C37/042 , Y10T428/2964
摘要： An element wire, an electric wire including the element wire or the element wires, and a process for producing an element wire are provided, by which ductility of a core wire consisting of the element wires can be improved. The element wire is made of metal, at least one element wire being coated with an electrically insulating coating so as to constitute an electric wire. The crystal grains constituting the entire element wire are fine isometric grains. In the process for producing the element wire, an electrically conductive material is subjected to drawing so as to reduce a diameter of the material and subsequently subjected to successive bending along a longitudinal direction of the material.
摘要翻译：提供元件线，包括元件线或元件线的电线，以及用于制造元件线的工艺，由此可以提高由元件线构成的芯线的延展性。元件线由金属制成，至少一个元件线被电绝缘涂层涂覆以构成电线。构成整个元件线的晶粒是细小的等轴晶粒。在制造元件线的过程中，对导电材料进行拉伸，以减小材料的直径，随后沿材料的纵向连续弯曲。

2. 发明授权

US07656215B2 Clock generator circuit, clock selector circuit, and semiconductor integrated circuit 有权
标题翻译：时钟发生器电路，时钟选择器电路和半导体集成电路
公开(公告)号：US07656215B2
公开(公告)日：2010-02-02
申请号：US12073332
申请日：2008-03-04
申请人： Nobuhiro Tsuji
发明人： Nobuhiro Tsuji
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit outputs a switching signal when detecting the abnormal waveform pulse in the second clock. A selector outputs the first clock instead of the second clock as the output clock based on the switching signal. A delay circuit delays the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector.
摘要翻译：时钟发生器电路提供输出时钟，而不会产生异常波形脉冲，导致其他功能电路故障。相位同步电路输出与第一时钟同步的第二时钟。选择器信号发生器电路在检测第二时钟中的异常波形脉冲时输出切换信号。 A选择器基于开关信号输出第一时钟而不是第二时钟作为输出时钟。延迟电路将第二时钟输入延迟到选择器，使得选择器将输出时钟从第二时钟切换到第一时钟，然后将异常波形脉冲输入到选择器。

3. 发明申请

US20070084529A1 HIGH STRENGTH AND HIGH DUCTILITY STEEL SHEET HAVING ULTRAFINE CRYSTALLINE GRAIN STRUCTURE OBTAINED BY LOW STRAIN PROCESSING AND ANNEALING OF ORDINARY LOW CARBON STEEL, AND A METHOD FOR PRODUCING THEREOF 审中-公开
标题翻译：具有通过低应变处理和常规低碳钢退火获得的超细晶粒结构的高强度和高强度钢板及其生产方法
公开(公告)号：US20070084529A1
公开(公告)日：2007-04-19
申请号：US11548532
申请日：2006-10-11
申请人： Yoshihiro Saito , Nobuhiro Tsuji , Rintaro Ueji
发明人： Yoshihiro Saito , Nobuhiro Tsuji , Rintaro Ueji
IPC分类号： C21D6/00
CPC分类号： C22C38/02 , C21D1/25 , C21D8/02 , C21D8/0236 , C21D8/0273 , C21D2201/00 , C21D2211/005 , C21D2211/008 , C22C38/04
摘要： A high strength and high ductility low carbon steel having a tensile strength of 800 MPa or more, an uniform elongation of 5% or more, and an elongation to failure of 20% or more which is produced by a method comprising subjecting an ordinary low carbon steel or an ordinary low carbon steel added with boron in an amount being 0.01% or less and effective for accelerating martensitic transformation to processing and heat treatment to prepare a product having coarser size of austenite crystal grains and then to water-quenching, to provide a steel product having a martensite phase in an amount of 90% or more, and subjecting the steel product to a low strain processing, specifically a cold rolling at a total rolling reduction in thickness of 20% or more and less than 80%, and to a low temperature annealing at 500° C. to 600° C., and a method for producing said high strength and high ductility low carbon steel.
摘要翻译：通过以下方法制造的拉伸强度为800MPa以上，均匀伸长率为5％以上，断裂伸长率为20％以上的高强度，高延展性的低碳钢，该方法包括使普通低碳钢或普通低碳钢，其添加量为0.01％以下，并且有效加速马氏体转变成加工和热处理，以制备具有较大尺寸的奥氏体晶粒的产品，然后进行水淬，从而提供具有90％以上的马氏体相的钢产品，并且对钢制品进行低应变加工，特别是在总轧制压下量为20％以上且小于80％的情况下的冷轧，以及在500℃至600℃的低温退火，以及用于生产所述高强度和高延展性低碳钢的方法。

4. 发明授权

US07063751B2 Semiconductor substrate formed by epitaxially filling a trench in a semiconductor substrate with a semiconductor material after smoothing the surface and rounding the corners 有权
标题翻译：半导体衬底通过在使表面平滑并使其四舍五入之后用半导体材料外延地填充半导体衬底中的沟槽而形成
公开(公告)号：US07063751B2
公开(公告)日：2006-06-20
申请号：US10132298
申请日：2002-04-26
申请人： Yasushi Urakami , Shoichi Yamauchi , Hitoshi Yamaguchi , Nobuhiro Tsuji
发明人： Yasushi Urakami , Shoichi Yamauchi , Hitoshi Yamaguchi , Nobuhiro Tsuji
IPC分类号： H01L29/12 , H01L29/30 , H01L21/20 , H01L21/36 , H01L29/04
CPC分类号： H01L21/763 , H01L21/30608 , H01L21/761
摘要： A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that the width of the mask opening width is greater than the width of the trench. After that, the inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished to complete the substrate.
摘要翻译：通过由形成在半导体衬底上的氧化硅膜构成的掩模，在半导体衬底中形成沟槽。然后，蚀刻掩模的开口部分的边缘部分，使得掩模开口宽度的宽度大于沟槽的宽度。之后，通过在低压下在非氧化或非氮化气氛中在1000℃左右的热处理使沟槽的内表面平滑化。然后，沟槽填充有外延膜。之后，抛光外延膜以完成基板。

5. 发明授权

US06836001B2 Semiconductor device having epitaxially-filled trench and method for manufacturing semiconductor device having epitaxially-filled trench 有权
标题翻译：具有外延填充沟槽的半导体器件和具有外延填充沟槽的半导体器件的制造方法
公开(公告)号：US06836001B2
公开(公告)日：2004-12-28
申请号：US10442196
申请日：2003-05-21
申请人： Shoichi Yamauchi , Hitoshi Yamaguchi , Jun Sakakibara , Nobuhiro Tsuji
发明人： Shoichi Yamauchi , Hitoshi Yamaguchi , Jun Sakakibara , Nobuhiro Tsuji
IPC分类号： H01L2904
CPC分类号： H01L29/781 , H01L29/045 , H01L29/0634 , H01L29/4232 , H01L29/4238 , H01L29/66674 , H01L29/7801 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.
摘要翻译：半导体器件包括半导体衬底和半导体层。半导体衬底具有作为Si {100}表面的主表面。基板在主表面具有沟槽。半导体层位于限定沟槽的表面上，以与半导体衬底具有共同的结晶平面。沟槽由底面，彼此面对的两个长侧壁表面和彼此相对的两个短侧壁表面限定。底表面和长侧壁表面是Si {100}表面。

6. 发明授权

US06406982B2 Method of improving epitaxially-filled trench by smoothing trench prior to filling 有权
标题翻译：通过在填充之前平滑沟槽来改善外延填充沟槽的方法
公开(公告)号：US06406982B2
公开(公告)日：2002-06-18
申请号：US09870705
申请日：2001-06-01
申请人： Yasushi Urakami , Shoichi Yamauchi , Toshio Sakakibara , Hitoshi Yamaguchi , Nobuhiro Tsuji
发明人： Yasushi Urakami , Shoichi Yamauchi , Toshio Sakakibara , Hitoshi Yamaguchi , Nobuhiro Tsuji
IPC分类号： H01L2120
CPC分类号： H01L21/763 , H01L21/30608 , H01L21/761
摘要： A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.
摘要翻译：通过由形成在半导体衬底上的氧化硅膜构成的掩模，在半导体衬底中形成沟槽。然后，蚀刻掩模的开口部分的边缘部分，使得其开口宽度比沟槽的宽度宽。之后，通过在低压下在非氧化或非氮化气氛中在1000℃左右的热处理使沟槽的内表面平滑化。然后，沟槽填充有外延膜。之后，对该外延膜进行研磨，得到半导体装置的半导体基板。

7. 发明申请

US20060046146A1 Method for producing non-expanded graphite powder 审中-公开
标题翻译：非膨胀石墨粉的制造方法
公开(公告)号：US20060046146A1
公开(公告)日：2006-03-02
申请号：US11208788
申请日：2005-08-23
申请人： Nobuhiro Tsuji , Hisanori Sugimoto
发明人： Nobuhiro Tsuji , Hisanori Sugimoto
IPC分类号： H01M4/62 , H01M4/50 , C01B31/04
CPC分类号： H01M4/625 , C01B32/20 , C01P2004/61 , C01P2006/11 , C01P2006/12 , H01M4/06 , H01M4/50
摘要： There is provided a new type of non-expanded graphite powder by peeling off a lamination plane within non-expanded graphite particles, which is useful as a conductive carbon material in a positive electrode mix for an alkaline manganese battery. The alkaline manganese battery has an excellent discharge property when the above non-expanded graphite powder are used as the conductive carbon material.
摘要翻译：通过在非膨胀石墨颗粒内剥离层压平面来提供新型的非膨胀石墨粉末，其可用作碱性锰电池正极混合物中的导电碳材料。当使用上述非膨胀石墨粉末作为导电碳材料时，碱锰电池具有优异的放电性能。

8. 发明申请

US20050045996A1 Semiconductor device having epitaxially-filled trench and method for manufacturing semiconductor device having epitaxially-filled trench 审中-公开
标题翻译：具有外延填充沟槽的半导体器件和具有外延填充沟槽的半导体器件的制造方法
公开(公告)号：US20050045996A1
公开(公告)日：2005-03-03
申请号：US10950423
申请日：2004-09-28
申请人： Shoichi Yamauchi , Hitoshi Yamaguchi , Jun Sakakibara , Nobuhiro Tsuji
发明人： Shoichi Yamauchi , Hitoshi Yamaguchi , Jun Sakakibara , Nobuhiro Tsuji
IPC分类号： H01L21/20 , H01L21/336 , H01L29/04 , H01L29/06 , H01L29/12 , H01L29/423 , H01L29/78 , H01L21/332 , H01L31/036
CPC分类号： H01L29/781 , H01L29/045 , H01L29/0634 , H01L29/4232 , H01L29/4238 , H01L29/66674 , H01L29/7801 , H01L29/7813
摘要： A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.
摘要翻译：半导体器件包括半导体衬底和半导体层。半导体衬底具有作为Si {100}表面的主表面。基板在主表面具有沟槽。半导体层位于限定沟槽的表面上，以与半导体衬底具有共同的结晶平面。沟槽由底面，彼此面对的两个长侧壁表面和彼此相对的两个短侧壁表面限定。底表面和长侧壁表面是Si {100}表面。

9. 发明申请

US20080213589A1 Element wire, electric wire and process for producing element wire 有权
标题翻译：元素线，电线和生产元素线的工艺
公开(公告)号：US20080213589A1
公开(公告)日：2008-09-04
申请号：US12073157
申请日：2008-02-29
申请人： Kenichi Hanazaki , Satoru Yoshinaga , Nobuhiro Tsuji
发明人： Kenichi Hanazaki , Satoru Yoshinaga , Nobuhiro Tsuji
IPC分类号： B32B15/02 , B05B5/12
CPC分类号： B21C23/26 , B21C1/00 , B21C37/042 , Y10T428/2964
摘要： An element wire, an electric wire including the element wire or the element wires, and a process for producing an element wire are provided, by which ductility of a core wire consisting of the element wires can be improved. The element wire is made of metal, at least one element wire being coated with an electrically insulating coating so as to constitute an electric wire. The crystal grains constituting the entire element wire are fine isometric grains. In the process for producing the element wire, an electrically conductive material is subjected to drawing so as to reduce a diameter of the material and subsequently subjected to successive bending along a longitudinal direction of the material.
摘要翻译：提供元件线，包括元件线或元件线的电线，以及用于制造元件线的工艺，由此可以提高由元件线构成的芯线的延展性。元件线由金属制成，至少一个元件线被电绝缘涂层涂覆以构成电线。构成整个元件线的晶粒是细小的等轴晶粒。在制造元件线的过程中，对导电材料进行拉伸，以减小材料的直径，随后沿材料的纵向连续弯曲。

10. 发明申请

US20110076830A1 METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE 有权
标题翻译：制造半导体基板的方法
公开(公告)号：US20110076830A1
公开(公告)日：2011-03-31
申请号：US12964141
申请日：2010-12-09
申请人： Syouji NOGAMI , Tomonori YAMAOKA , Shoichi YAMAUCHI , Nobuhiro TSUJI , Toshiyuki MORISHITA
发明人： Syouji NOGAMI , Tomonori YAMAOKA , Shoichi YAMAUCHI , Nobuhiro TSUJI , Toshiyuki MORISHITA
IPC分类号： H01L21/308
CPC分类号： H01L21/30604 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L21/02664 , H01L21/308 , H01L23/544 , H01L29/0634 , H01L29/66712 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N+-type substrate. This trench is used to leave voids after the formation of an N−-type layer. Then, the voids formed in the N+-type substrate can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.
摘要翻译：提供了一种半导体衬底，其中形成了即使在通过外延膜的平坦化形成杂质扩散层之后也可用于分配的对准标记。在N +型衬底的取向区域中形成沟槽。这种沟槽用于在形成N型层之后留下空隙。然后，可以使用形成在N +型衬底中的空隙作为对准标记。因此，可以使用这样的半导体衬底在制造半导体器件的后续步骤中提供对准。因此，构成半导体装置的各个部件可以精确地形成在期望的位置。

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